Post on 25-Mar-2020
Mathematical challenges in VLSI chip design
Thanos Antoulas
Rice U & Jacobs U
email: aca@rice.edu & a.c.antoulas@jacobs-university.de
MOR Symposium, TU Eindhoven, 23 November 2007
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 1 / 30
Contents
1 Chip design: Moore’s Law
2 Issues in chip design
Signal delayHeat generationMixed-signal designs
3 Proposed methodologies
PhotonicsPlasmonicsCarbon nanotubesS-parameter design
4 Conclusions and mathematical challenges
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 2 / 30
Contents
1 Chip design: Moore’s Law
2 Issues in chip design
Signal delayHeat generationMixed-signal designs
3 Proposed methodologies
PhotonicsPlasmonicsCarbon nanotubesS-parameter design
4 Conclusions and mathematical challenges
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 2 / 30
Contents
1 Chip design: Moore’s Law
2 Issues in chip design
Signal delayHeat generationMixed-signal designs
3 Proposed methodologies
PhotonicsPlasmonicsCarbon nanotubesS-parameter design
4 Conclusions and mathematical challenges
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 2 / 30
Contents
1 Chip design: Moore’s Law
2 Issues in chip design
Signal delayHeat generationMixed-signal designs
3 Proposed methodologies
PhotonicsPlasmonicsCarbon nanotubesS-parameter design
4 Conclusions and mathematical challenges
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 2 / 30
Transistor revolution
Transistor: Bardeen (Bell Labs) 1947
Bipolar transistor: Schockley 1949
Bipolar logic gate: Harris 1956
Monolithic IC (integrated circuit): Jack Kilby 1959
Commercial IC logic gates: Fairchild 1960
TTL (transistor-transistor logic): 1962 into the 1990s
ECL (emitter-coupled logic): 1974 into the 1980s
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 3 / 30
VLSI Chips and Moore’s LawIn 1965 Gordon Moore predicted that the number of transistors that canbe integrated on a die would double every 18 months
⇒ exponential growth.
1960’s: IC 1971: Intel 4004 2001: Intel Pentium IV10µ details 0.18µ details2300 components 42M components64KHz speed 2GHz speed
2km interconnect7 layers
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 4 / 30
Moore’s Law: doubling of the number of transistors every 18 months
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 5 / 30
Scaling in integrated circuits
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 6 / 30
Some issues
Signal delay/Crosstalk
Heat generation
Complexity in mixed-signal design
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 7 / 30
Some issues
Signal delay/Crosstalk
Heat generation
Complexity in mixed-signal design
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 7 / 30
Some issues
Signal delay/Crosstalk
Heat generation
Complexity in mixed-signal design
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 7 / 30
Signal delay
Typical GateDelay
0.1
1.0
Del
ay (n
s)
1.01.3 0.8 0.30.5Technology (μm)
0.1 0.08
Average WiringDelay
≈ 0.25 μm
Today’s Technology: 65 nm
65nm technology: gate delay < interconnect delay!
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 8 / 30
Signal delay
Interconnect simulation: required to verify that internalelectromagnetic fields do not significantly delay or distort circuitsignals. Therefore interconnections must be modeled⇒ resultingmodels very complex: using PEEC methods (discretization ofMaxwell’s equations): n ≈ 105 · · · 107
Silicon bulk (5139 elements) and
metal lines (51682 elements)
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 9 / 30
Heat generationKitchen stove: 18cm diameter, P≈ 1.5kW ⇒ 6W/cm2
Pentium IV: Area≈ 2cm2, P≈ 88W ⇒ 40W/cm2
Conclusion: According to the 2006 ITRS, at the present rate ofminiaturization, the current technology can be sustained for a few more years(until the feature size reaches 45nm).
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 10 / 30
Heat generationKitchen stove: 18cm diameter, P≈ 1.5kW ⇒ 6W/cm2
Pentium IV: Area≈ 2cm2, P≈ 88W ⇒ 40W/cm2
Conclusion: According to the 2006 ITRS, at the present rate ofminiaturization, the current technology can be sustained for a few more years(until the feature size reaches 45nm).
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 10 / 30
Heat generationKitchen stove: 18cm diameter, P≈ 1.5kW ⇒ 6W/cm2
Pentium IV: Area≈ 2cm2, P≈ 88W ⇒ 40W/cm2
Conclusion: According to the 2006 ITRS, at the present rate ofminiaturization, the current technology can be sustained for a few more years(until the feature size reaches 45nm).
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 10 / 30
Heat generationKitchen stove: 18cm diameter, P≈ 1.5kW ⇒ 6W/cm2
Pentium IV: Area≈ 2cm2, P≈ 88W ⇒ 40W/cm2
Conclusion: According to the 2006 ITRS, at the present rate ofminiaturization, the current technology can be sustained for a few more years(until the feature size reaches 45nm).
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 10 / 30
Potential new chip technology: Photonics
• Daunting challenges to increase processor speed:
thermal and signal delay
• Optical interconnects: many advantages but their implementationis hampered by the large size mismatch between the electronic anddielectric photonic components (≈ half wavelength of light)⇒ tend tobe one or two orders of magnitude larger than their nanoscaleelectronic components (nanoscale electronics and microscalephotonics).
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 11 / 30
Potential new chip technology: Photonics
• Daunting challenges to increase processor speed:
thermal and signal delay
• Optical interconnects: many advantages but their implementationis hampered by the large size mismatch between the electronic anddielectric photonic components (≈ half wavelength of light)⇒ tend tobe one or two orders of magnitude larger than their nanoscaleelectronic components (nanoscale electronics and microscalephotonics).
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 11 / 30
New proposed chip technology: Plasmonics
• Plasmonics: new device technology.
Metal nanostructures possess the right combination of electronic andoptical properties. The metals used for electrical interconnection (Cu,Al) allow the excitation of surface plasmon-polaritons (SPPs). Theseare electromagnetic waves that propagate along a metal-dielectricinterface, and can be viewed as a special type of light wave. Thesemetalic interconnects act therefore as tiny waveguides, calledplasmonic waveguides. The dimension normal to the surface can bemuch smaller than the wavelength of light.
Fig. 1 An SPP propagating along a metal-dielectric interface. These waves are transverse magnetic in nature. Their electromagnetic field intensity is highest at thesurface and decays exponentially away from the interface. From an engineering standpoint, an SPP can be viewed as a special type of light wave propagating alongthe metal surface.
Plasmonics: the next chip-scale technology REVIEW FEATURE
JULY-AUGUST 2006 | VOLUME 9 | NUMBER 7-8 21
present some of our recent studies on plasmonic structures and
conclude by providing an assessment of the potential opportunities and
limitations for Si chip-scale plasmonics.
Plasmonics as a new device technologyMetal nanostructures may possess exactly the right combination of
electronic and optical properties to tackle the issues outlined above
and realize the dream of significantly faster processing speeds. The
metals commonly used in electrical interconnection such as Cu and Al
allow the excitation of surface plasmon-polaritons (SPPs). SPPs are
electromagnetic waves that propagate along a metal-dielectric
interface and are coupled to the free electrons in the metal
(Fig. 1)9-11.
From an engineering standpoint, an SPP can be viewed as a special
type of light wave. The metallic interconnects that support such waves
thus serve as tiny optical waveguides termed plasmonic waveguides.
The notion that the optical mode (‘light beam’) diameter normal to the
metal interface can be significantly smaller than the wavelength of
light12 has generated significant excitement and sparked the dream
that one day we will be able to interface nanoscale electronics with
similarly sized optical (plasmonic) devices.
It is important to realize that, with the latest advances in
electromagnetic simulations and current complementary metal-oxide
semiconductor (CMOS)-compatible fabrication techniques, a variety
of functional plasmonic structures can be designed and fabricated in a
Si foundry right now. Current Si-based integrated circuit technology
already uses nanoscale metallic structures, such as Cu and Al
interconnects, to route electronic signals between transistors on a chip.
This mature processing technology can thus be used to our advantage
in integrating plasmonic devices with their electronic and dielectric
photonic counterparts. In some cases, plasmonic waveguides may even
perform a dual function and simultaneously carry both optical and
electrical signals, giving rise to exciting new capabilities13.
Imaging SPPs with a photon scanningtunneling microscopeIn order to study the propagation of SPPs, we constructed a photon
scanning tunneling microscope (PSTM)14 by modifying a commercially
available scanning near-field optical microscope. PSTMs are the tool of
choice for characterizing SPP propagation along extended films as well
as metal stripe waveguides15-17. Fig. 2a shows how a microscope
objective at the heart of our PSTM can be used to focus a laser beam
onto a metal film at a well-defined angle and thereby launch an SPP
along the top metal surface. This method of exciting SPPs makes use of
the well-known Kretschmann geometry that enables phase matching of
the free space excitation beam and the SPP18.
A sharp, metal-coated pyramidal tip (Figs. 2b and 2c) is used to tap
into the guided SPP wave locally and scatter light toward a far-field
detector. These particular tips have a nanoscale aperture at the top of
the pyramid through which light can be collected. The scattered light is
then detected with a photomultiplier tube. The signal provides a
measure of the local light intensity right underneath the tip and, by
scanning the tip over the metal surface, the propagation of SPPs can be
imaged.
The operation of the PSTM can be illustrated by investigating the
propagation of SPPs on a patterned Au film (Fig. 2d). Here, a focused
ion beam (FIB) was used to define a series of parallel grooves, which
serve as a Bragg grating to reflect SPP waves. Fig. 2e shows a PSTM
image of an SPP wave excited with a 780 nm wavelength laser and
directed toward the Bragg grating. The back reflection of the SPP from
the grating results in the standing wave interference pattern observed
in the image. From this type of experiment the wavelength of SPPs
can be determined in a straightforward manner and compared to
theory.
The PSTM can also be used to image SPP propagation directly in
plasmonic structures and devices of more complex architecture to
determine their behavior. This is quite different from typical
mt97_8p20_27.qxd 06/15/2006 09:35 Page 21
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 12 / 30
New proposed chip technology: Plasmonics
• Plasmonics: new device technology.
Metal nanostructures possess the right combination of electronic andoptical properties. The metals used for electrical interconnection (Cu,Al) allow the excitation of surface plasmon-polaritons (SPPs). Theseare electromagnetic waves that propagate along a metal-dielectricinterface, and can be viewed as a special type of light wave. Thesemetalic interconnects act therefore as tiny waveguides, calledplasmonic waveguides. The dimension normal to the surface can bemuch smaller than the wavelength of light.
Fig. 1 An SPP propagating along a metal-dielectric interface. These waves are transverse magnetic in nature. Their electromagnetic field intensity is highest at thesurface and decays exponentially away from the interface. From an engineering standpoint, an SPP can be viewed as a special type of light wave propagating alongthe metal surface.
Plasmonics: the next chip-scale technology REVIEW FEATURE
JULY-AUGUST 2006 | VOLUME 9 | NUMBER 7-8 21
present some of our recent studies on plasmonic structures and
conclude by providing an assessment of the potential opportunities and
limitations for Si chip-scale plasmonics.
Plasmonics as a new device technologyMetal nanostructures may possess exactly the right combination of
electronic and optical properties to tackle the issues outlined above
and realize the dream of significantly faster processing speeds. The
metals commonly used in electrical interconnection such as Cu and Al
allow the excitation of surface plasmon-polaritons (SPPs). SPPs are
electromagnetic waves that propagate along a metal-dielectric
interface and are coupled to the free electrons in the metal
(Fig. 1)9-11.
From an engineering standpoint, an SPP can be viewed as a special
type of light wave. The metallic interconnects that support such waves
thus serve as tiny optical waveguides termed plasmonic waveguides.
The notion that the optical mode (‘light beam’) diameter normal to the
metal interface can be significantly smaller than the wavelength of
light12 has generated significant excitement and sparked the dream
that one day we will be able to interface nanoscale electronics with
similarly sized optical (plasmonic) devices.
It is important to realize that, with the latest advances in
electromagnetic simulations and current complementary metal-oxide
semiconductor (CMOS)-compatible fabrication techniques, a variety
of functional plasmonic structures can be designed and fabricated in a
Si foundry right now. Current Si-based integrated circuit technology
already uses nanoscale metallic structures, such as Cu and Al
interconnects, to route electronic signals between transistors on a chip.
This mature processing technology can thus be used to our advantage
in integrating plasmonic devices with their electronic and dielectric
photonic counterparts. In some cases, plasmonic waveguides may even
perform a dual function and simultaneously carry both optical and
electrical signals, giving rise to exciting new capabilities13.
Imaging SPPs with a photon scanningtunneling microscopeIn order to study the propagation of SPPs, we constructed a photon
scanning tunneling microscope (PSTM)14 by modifying a commercially
available scanning near-field optical microscope. PSTMs are the tool of
choice for characterizing SPP propagation along extended films as well
as metal stripe waveguides15-17. Fig. 2a shows how a microscope
objective at the heart of our PSTM can be used to focus a laser beam
onto a metal film at a well-defined angle and thereby launch an SPP
along the top metal surface. This method of exciting SPPs makes use of
the well-known Kretschmann geometry that enables phase matching of
the free space excitation beam and the SPP18.
A sharp, metal-coated pyramidal tip (Figs. 2b and 2c) is used to tap
into the guided SPP wave locally and scatter light toward a far-field
detector. These particular tips have a nanoscale aperture at the top of
the pyramid through which light can be collected. The scattered light is
then detected with a photomultiplier tube. The signal provides a
measure of the local light intensity right underneath the tip and, by
scanning the tip over the metal surface, the propagation of SPPs can be
imaged.
The operation of the PSTM can be illustrated by investigating the
propagation of SPPs on a patterned Au film (Fig. 2d). Here, a focused
ion beam (FIB) was used to define a series of parallel grooves, which
serve as a Bragg grating to reflect SPP waves. Fig. 2e shows a PSTM
image of an SPP wave excited with a 780 nm wavelength laser and
directed toward the Bragg grating. The back reflection of the SPP from
the grating results in the standing wave interference pattern observed
in the image. From this type of experiment the wavelength of SPPs
can be determined in a straightforward manner and compared to
theory.
The PSTM can also be used to image SPP propagation directly in
plasmonic structures and devices of more complex architecture to
determine their behavior. This is quite different from typical
mt97_8p20_27.qxd 06/15/2006 09:35 Page 21
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 12 / 30
Plasmonics: Modeling of nanoparticles
= ZNanoparticleZ1 Z3Nanodimer
Z2 NonplanarPlasmonicWaveguide
Z3 Z5 Z7Z1
Z2Z2 Z2
Impedance
Impedance
Z impedance of nanoparticle involving spherical Bessel and Hankel functions⇒improvement over diplole approximation of a nanoparticle
RLC Model
DipoleApproximation
Dipole ApproxRLC Model
Metal nanoparticle RLCmodel error compared withexact solution (Mie theory)
Conceptual Characterization ofNon-Planar Waveguide
M12
1 3 5 7
82 4 6
M34 M56 M78
M24 M46 M68
M13 M35 M57
M14 M23 M36 M45M58 M67
+=E(w, a) x A(w, a) x B u
Frequency (w) & Size (a) dependent state spacerepresentation
.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 13 / 30
Plasmonics: Modeling of nanoparticles
= ZNanoparticleZ1 Z3Nanodimer
Z2 NonplanarPlasmonicWaveguide
Z3 Z5 Z7Z1
Z2Z2 Z2
Impedance
Impedance
Z impedance of nanoparticle involving spherical Bessel and Hankel functions⇒improvement over diplole approximation of a nanoparticle
RLC Model
DipoleApproximation
Dipole ApproxRLC Model
Metal nanoparticle RLCmodel error compared withexact solution (Mie theory)
Conceptual Characterization ofNon-Planar Waveguide
M12
1 3 5 7
82 4 6
M34 M56 M78
M24 M46 M68
M13 M35 M57
M14 M23 M36 M45M58 M67
+=E(w, a) x A(w, a) x B u
Frequency (w) & Size (a) dependent state spacerepresentation
.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 13 / 30
Plasmonics: Modeling of nanoparticles
= ZNanoparticleZ1 Z3Nanodimer
Z2 NonplanarPlasmonicWaveguide
Z3 Z5 Z7Z1
Z2Z2 Z2
Impedance
Impedance
Z impedance of nanoparticle involving spherical Bessel and Hankel functions⇒improvement over diplole approximation of a nanoparticle
RLC Model
DipoleApproximation
Dipole ApproxRLC Model
Metal nanoparticle RLCmodel error compared withexact solution (Mie theory)
Conceptual Characterization ofNon-Planar Waveguide
M12
1 3 5 7
82 4 6
M34 M56 M78
M24 M46 M68
M13 M35 M57
M14 M23 M36 M45M58 M67
+=E(w, a) x A(w, a) x B u
Frequency (w) & Size (a) dependent state spacerepresentation
.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 13 / 30
Plasmonics: Modeling of nanoparticles
= ZNanoparticleZ1 Z3Nanodimer
Z2 NonplanarPlasmonicWaveguide
Z3 Z5 Z7Z1
Z2Z2 Z2
Impedance
Impedance
Z impedance of nanoparticle involving spherical Bessel and Hankel functions⇒improvement over diplole approximation of a nanoparticle
RLC Model
DipoleApproximation
Dipole ApproxRLC Model
Metal nanoparticle RLCmodel error compared withexact solution (Mie theory)
Conceptual Characterization ofNon-Planar Waveguide
M12
1 3 5 7
82 4 6
M34 M56 M78
M24 M46 M68
M13 M35 M57
M14 M23 M36 M45M58 M67
+=E(w, a) x A(w, a) x B u
Frequency (w) & Size (a) dependent state spacerepresentation
.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 13 / 30
Operating speed vs. Feature size
Electronics: the past
Photonics
The present
Plasmonics
-
6
1mm 100µm 10µm 1µm 100nm 10nm
1kHz
1MHz
1GHz
1THz
Feature size
Operatingspeed
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 14 / 30
Operating speed vs. Feature size
Electronics: the past
Photonics
The present
Plasmonics
-
6
1mm 100µm 10µm 1µm 100nm 10nm
1kHz
1MHz
1GHz
1THz
Feature size
Operatingspeed
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 14 / 30
Operating speed vs. Feature size
Electronics: the past
Photonics
The present
Plasmonics
-
6
1mm 100µm 10µm 1µm 100nm 10nm
1kHz
1MHz
1GHz
1THz
Feature size
Operatingspeed
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 14 / 30
Operating speed vs. Feature size
Electronics: the past
Photonics
The present
Plasmonics
-
6
1mm 100µm 10µm 1µm 100nm 10nm
1kHz
1MHz
1GHz
1THz
Feature size
Operatingspeed
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 14 / 30
Operating speed vs. Feature size
Electronics: the past
Photonics
The present
Plasmonics
-
6
1mm 100µm 10µm 1µm 100nm 10nm
1kHz
1MHz
1GHz
1THz
Feature size
Operatingspeed
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 14 / 30
Proposed interconnect solution: carbon nanotubes
• CNTs have been proposed as a replacement for on-chip copperinterconnects due to their large conductivity and current carrying capabilities.
• Advantages over copper:
1 Resistance. CNTs have lower resistance than standard copper
2 Current density. Single-wall Carbon Nanotubes (SWCNTs) withdiameters ranging from 0.4nm to 4nm have been reported, with currentdensities as large as 1010A/cm2, versus traditional metallic interconnectwith typical current densities on the order of 105A/cm2.
3 Electromigration. CNTs are much less susceptible to electromigrationproblems with thermal conductivity more than 10 times higher thanconventional copper.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 15 / 30
Proposed interconnect solution: carbon nanotubes
• CNTs have been proposed as a replacement for on-chip copperinterconnects due to their large conductivity and current carrying capabilities.
• Advantages over copper:
1 Resistance. CNTs have lower resistance than standard copper
2 Current density. Single-wall Carbon Nanotubes (SWCNTs) withdiameters ranging from 0.4nm to 4nm have been reported, with currentdensities as large as 1010A/cm2, versus traditional metallic interconnectwith typical current densities on the order of 105A/cm2.
3 Electromigration. CNTs are much less susceptible to electromigrationproblems with thermal conductivity more than 10 times higher thanconventional copper.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 15 / 30
Proposed interconnect solution: carbon nanotubes
• CNTs have been proposed as a replacement for on-chip copperinterconnects due to their large conductivity and current carrying capabilities.
• Advantages over copper:
1 Resistance. CNTs have lower resistance than standard copper
2 Current density. Single-wall Carbon Nanotubes (SWCNTs) withdiameters ranging from 0.4nm to 4nm have been reported, with currentdensities as large as 1010A/cm2, versus traditional metallic interconnectwith typical current densities on the order of 105A/cm2.
3 Electromigration. CNTs are much less susceptible to electromigrationproblems with thermal conductivity more than 10 times higher thanconventional copper.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 15 / 30
Proposed interconnect solution: carbon nanotubes
• CNTs have been proposed as a replacement for on-chip copperinterconnects due to their large conductivity and current carrying capabilities.
• Advantages over copper:
1 Resistance. CNTs have lower resistance than standard copper
2 Current density. Single-wall Carbon Nanotubes (SWCNTs) withdiameters ranging from 0.4nm to 4nm have been reported, with currentdensities as large as 1010A/cm2, versus traditional metallic interconnectwith typical current densities on the order of 105A/cm2.
3 Electromigration. CNTs are much less susceptible to electromigrationproblems with thermal conductivity more than 10 times higher thanconventional copper.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 15 / 30
Proposed interconnect solution: carbon nanotubes
• CNTs have been proposed as a replacement for on-chip copperinterconnects due to their large conductivity and current carrying capabilities.
• Advantages over copper:
1 Resistance. CNTs have lower resistance than standard copper
2 Current density. Single-wall Carbon Nanotubes (SWCNTs) withdiameters ranging from 0.4nm to 4nm have been reported, with currentdensities as large as 1010A/cm2, versus traditional metallic interconnectwith typical current densities on the order of 105A/cm2.
3 Electromigration. CNTs are much less susceptible to electromigrationproblems with thermal conductivity more than 10 times higher thanconventional copper.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 15 / 30
Carbon nanotubes: modeling
Ground Plane
CarbonNanotube
h
d
Copper Interconnect Carbon Nanotube Interconnect
Analytical model of SWCNT: transmission line involving magnetic and kinetic inductance,as well as electrostatic and quantum capacitance.
RC+RCNT LM+LK LM+LK RC+RCNT
CQ
CE
CQ
CE
Driver Load
Single wall carbon nanotube equivalent model
+=E x A x B u.
EM Filed Solver with MQS,EMQS and Full Wave Analysis
CNTs Based Interconnect Bundles
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 16 / 30
Carbon nanotubes: modeling
Ground Plane
CarbonNanotube
h
d
Copper Interconnect Carbon Nanotube Interconnect
Analytical model of SWCNT: transmission line involving magnetic and kinetic inductance,as well as electrostatic and quantum capacitance.
RC+RCNT LM+LK LM+LK RC+RCNT
CQ
CE
CQ
CE
Driver Load
Single wall carbon nanotube equivalent model
+=E x A x B u.
EM Filed Solver with MQS,EMQS and Full Wave Analysis
CNTs Based Interconnect Bundles
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 16 / 30
Carbon nanotubes: modeling
Ground Plane
CarbonNanotube
h
d
Copper Interconnect Carbon Nanotube Interconnect
Analytical model of SWCNT: transmission line involving magnetic and kinetic inductance,as well as electrostatic and quantum capacitance.
RC+RCNT LM+LK LM+LK RC+RCNT
CQ
CE
CQ
CE
Driver Load
Single wall carbon nanotube equivalent model
+=E x A x B u.
EM Filed Solver with MQS,EMQS and Full Wave Analysis
CNTs Based Interconnect Bundles
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 16 / 30
CNT model
Magnetic inductance:
LM =µ
2πcosh−1
(2hd
)≈ µ
2πln(
hd
).
Kinetic inductance: kinetic energy due to net movement of charge
LK =h
2e2vF
Electrostatic capacitance between wire and ground:
CE =2πε
cosh−1(2h/d)
Quantum capacitance: energy to add electron at given quantum state
CQ =2e2
hvF
where: µ is the material permeability, h is the height of the nanotube above ground, d is the diameter, h is Planck’s constant,e is the charge of an electron, vF is the Fermi velocity in graphite≈ 8.105m/s, and ε is the material permittivity.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 17 / 30
CNT modelMagnetic inductance:
LM =µ
2πcosh−1
(2hd
)≈ µ
2πln(
hd
).
Kinetic inductance: kinetic energy due to net movement of charge
LK =h
2e2vF
Electrostatic capacitance between wire and ground:
CE =2πε
cosh−1(2h/d)
Quantum capacitance: energy to add electron at given quantum state
CQ =2e2
hvF
where: µ is the material permeability, h is the height of the nanotube above ground, d is the diameter, h is Planck’s constant,e is the charge of an electron, vF is the Fermi velocity in graphite≈ 8.105m/s, and ε is the material permittivity.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 17 / 30
CNT modelMagnetic inductance:
LM =µ
2πcosh−1
(2hd
)≈ µ
2πln(
hd
).
Kinetic inductance: kinetic energy due to net movement of charge
LK =h
2e2vF
Electrostatic capacitance between wire and ground:
CE =2πε
cosh−1(2h/d)
Quantum capacitance: energy to add electron at given quantum state
CQ =2e2
hvF
where: µ is the material permeability, h is the height of the nanotube above ground, d is the diameter, h is Planck’s constant,e is the charge of an electron, vF is the Fermi velocity in graphite≈ 8.105m/s, and ε is the material permittivity.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 17 / 30
CNT modelMagnetic inductance:
LM =µ
2πcosh−1
(2hd
)≈ µ
2πln(
hd
).
Kinetic inductance: kinetic energy due to net movement of charge
LK =h
2e2vF
Electrostatic capacitance between wire and ground:
CE =2πε
cosh−1(2h/d)
Quantum capacitance: energy to add electron at given quantum state
CQ =2e2
hvF
where: µ is the material permeability, h is the height of the nanotube above ground, d is the diameter, h is Planck’s constant,e is the charge of an electron, vF is the Fermi velocity in graphite≈ 8.105m/s, and ε is the material permittivity.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 17 / 30
CNT modelMagnetic inductance:
LM =µ
2πcosh−1
(2hd
)≈ µ
2πln(
hd
).
Kinetic inductance: kinetic energy due to net movement of charge
LK =h
2e2vF
Electrostatic capacitance between wire and ground:
CE =2πε
cosh−1(2h/d)
Quantum capacitance: energy to add electron at given quantum state
CQ =2e2
hvF
where: µ is the material permeability, h is the height of the nanotube above ground, d is the diameter, h is Planck’s constant,e is the charge of an electron, vF is the Fermi velocity in graphite≈ 8.105m/s, and ε is the material permittivity.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 17 / 30
On-chip analog electronics
Chips for communication systems consist of large analog and RF blocks. Toavoid costly re-fabrication, a verification cycle is developed for simulation anddesign optimization. A common approach to this verification is to replace thecircuit block layout by systems of equations and subsequently use theiraccurate approximants for system simulation.
Methodology. An input-output approach for modeling of the analog systemscan be employed. It treats them as black boxes. In the linear passive case,this leads to identification problems using
multi-port S-parameters
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 18 / 30
On-chip analog electronics
Chips for communication systems consist of large analog and RF blocks. Toavoid costly re-fabrication, a verification cycle is developed for simulation anddesign optimization. A common approach to this verification is to replace thecircuit block layout by systems of equations and subsequently use theiraccurate approximants for system simulation.
Methodology. An input-output approach for modeling of the analog systemscan be employed. It treats them as black boxes. In the linear passive case,this leads to identification problems using
multi-port S-parameters
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 18 / 30
On-chip analog electronics
Chips for communication systems consist of large analog and RF blocks. Toavoid costly re-fabrication, a verification cycle is developed for simulation anddesign optimization. A common approach to this verification is to replace thecircuit block layout by systems of equations and subsequently use theiraccurate approximants for system simulation.
Methodology. An input-output approach for modeling of the analog systemscan be employed. It treats them as black boxes. In the linear passive case,this leads to identification problems using
multi-port S-parameters
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 18 / 30
Measurement of S-parameters
VNA (Vector Network Analyzer) – Magnitude of S-parameters for 2 ports
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 19 / 30
Analysis of S-parameter identification
Assume for simplicity that the given data are scalar:
(si , φi), i = 1,2, · · · ,N, si 6= sj , i 6= j
Find H(s) = n(s)d(s) such that H(si) = φi , i = 1,2, · · · ,N,
and n,d: coprime polynomials.
Main tool: Loewner matrix. Divide the data in disjoint sets:(λi ,wi), i = 1,2, · · · , k , (µj , vj), j = 1,2, · · · ,q, k + q = N:
L =
w1−v1λ1−µ1
· · · w1−vqλ1−µq
.... . .
...wk−v1λk−µ1
· · · wk−vqλk−µq
∈ Ck×q
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 20 / 30
Analysis of S-parameter identification
Assume for simplicity that the given data are scalar:
(si , φi), i = 1,2, · · · ,N, si 6= sj , i 6= j
Find H(s) = n(s)d(s) such that H(si) = φi , i = 1,2, · · · ,N,
and n,d: coprime polynomials.
Main tool: Loewner matrix. Divide the data in disjoint sets:(λi ,wi), i = 1,2, · · · , k , (µj , vj), j = 1,2, · · · ,q, k + q = N:
L =
w1−v1λ1−µ1
· · · w1−vqλ1−µq
.... . .
...wk−v1λk−µ1
· · · wk−vqλk−µq
∈ Ck×q
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 20 / 30
Analysis of S-parameter identification
Assume for simplicity that the given data are scalar:
(si , φi), i = 1,2, · · · ,N, si 6= sj , i 6= j
Find H(s) = n(s)d(s) such that H(si) = φi , i = 1,2, · · · ,N,
and n,d: coprime polynomials.
Main tool: Loewner matrix. Divide the data in disjoint sets:(λi ,wi), i = 1,2, · · · , k , (µj , vj), j = 1,2, · · · ,q, k + q = N:
L =
w1−v1λ1−µ1
· · · w1−vqλ1−µq
.... . .
...wk−v1λk−µ1
· · · wk−vqλk−µq
∈ Ck×q
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 20 / 30
General framework – tangential interpolation
Given: • right data: (λi ; ri ,wi ), i = 1, · · · , k
• left data: (µj ; `j ,vj ), j = 1, · · · ,q.
We assume for simplicity that all points are distinct.
Problem: Find rational p ×m matrices H(s), such that
H(λi )ri = wi `jH(µj ) = vj
Right data:
Λ =
λ1. . .
λk
∈ Ck×k ,R = [r1 r2, · · · rk ] ∈ Cm×k ,
W = [w1 w2 · · · wk ] ∈ Cp×k
Left data:
M =
µ1. . .
µq
∈Cq×q,L =
`1...`q
∈Cq×p,V =
v1...
vq
∈ Cq×m
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 21 / 30
General framework – tangential interpolationGiven: • right data: (λi ; ri ,wi ), i = 1, · · · , k
• left data: (µj ; `j ,vj ), j = 1, · · · ,q.
We assume for simplicity that all points are distinct.
Problem: Find rational p ×m matrices H(s), such that
H(λi )ri = wi `jH(µj ) = vj
Right data:
Λ =
λ1. . .
λk
∈ Ck×k ,R = [r1 r2, · · · rk ] ∈ Cm×k ,
W = [w1 w2 · · · wk ] ∈ Cp×k
Left data:
M =
µ1. . .
µq
∈Cq×q,L =
`1...`q
∈Cq×p,V =
v1...
vq
∈ Cq×m
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 21 / 30
General framework – tangential interpolationGiven: • right data: (λi ; ri ,wi ), i = 1, · · · , k
• left data: (µj ; `j ,vj ), j = 1, · · · ,q.
We assume for simplicity that all points are distinct.
Problem: Find rational p ×m matrices H(s), such that
H(λi )ri = wi `jH(µj ) = vj
Right data:
Λ =
λ1. . .
λk
∈ Ck×k ,R = [r1 r2, · · · rk ] ∈ Cm×k ,
W = [w1 w2 · · · wk ] ∈ Cp×k
Left data:
M =
µ1. . .
µq
∈Cq×q,L =
`1...`q
∈Cq×p,V =
v1...
vq
∈ Cq×m
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 21 / 30
General framework – tangential interpolationGiven: • right data: (λi ; ri ,wi ), i = 1, · · · , k
• left data: (µj ; `j ,vj ), j = 1, · · · ,q.
We assume for simplicity that all points are distinct.
Problem: Find rational p ×m matrices H(s), such that
H(λi )ri = wi `jH(µj ) = vj
Right data:
Λ =
λ1. . .
λk
∈ Ck×k ,R = [r1 r2, · · · rk ] ∈ Cm×k ,
W = [w1 w2 · · · wk ] ∈ Cp×k
Left data:
M =
µ1. . .
µq
∈Cq×q,L =
`1...`q
∈Cq×p,V =
v1...
vq
∈ Cq×m
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 21 / 30
General framework – tangential interpolationGiven: • right data: (λi ; ri ,wi ), i = 1, · · · , k
• left data: (µj ; `j ,vj ), j = 1, · · · ,q.
We assume for simplicity that all points are distinct.
Problem: Find rational p ×m matrices H(s), such that
H(λi )ri = wi `jH(µj ) = vj
Right data:
Λ =
λ1. . .
λk
∈ Ck×k ,R = [r1 r2, · · · rk ] ∈ Cm×k ,
W = [w1 w2 · · · wk ] ∈ Cp×k
Left data:
M =
µ1. . .
µq
∈Cq×q,L =
`1...`q
∈Cq×p,V =
v1...
vq
∈ Cq×m
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 21 / 30
General framework – tangential interpolation
Input-output data. The Loewner matrix L satisfies
LΛ−ML = VR− LW
and therefore
L =
v1r1−`1w1λ1−µ1
· · · v1rk−`1wkλ1−µk
.... . .
...vqr1−`qw1λq−µ1
· · · vqrk−`qwkλq−µk
∈ Cq×k
Recall:
H(λi)ri = wi , `jH(µj) = vj
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 22 / 30
General framework – tangential interpolation
Input-output data. The Loewner matrix L satisfies
LΛ−ML = VR− LW
and therefore
L =
v1r1−`1w1λ1−µ1
· · · v1rk−`1wkλ1−µk
.... . .
...vqr1−`qw1λq−µ1
· · · vqrk−`qwkλq−µk
∈ Cq×k
Recall:
H(λi)ri = wi , `jH(µj) = vj
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 22 / 30
The shifted Loewner matrix
The shifted Loewner matrix, σL, is the Loewner matrix associatedto sH(s).
σL =
λ1v1r1−`1w1µ1
λ1−µ1· · · λ1v1rk−`1wkµk
λ1−µk...
. . ....
λqvqr1−`qw1µ1λq−µ1
· · · λqvqrk−`qwkµkλq−µk
∈ Cq×k
σL satisfiesσLM − ΛσL = LWM − ΛVR
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 23 / 30
The shifted Loewner matrix
The shifted Loewner matrix, σL, is the Loewner matrix associatedto sH(s).
σL =
λ1v1r1−`1w1µ1
λ1−µ1· · · λ1v1rk−`1wkµk
λ1−µk...
. . ....
λqvqr1−`qw1µ1λq−µ1
· · · λqvqrk−`qwkµkλq−µk
∈ Cq×k
σL satisfiesσLM − ΛσL = LWM − ΛVR
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 23 / 30
The shifted Loewner matrix
The shifted Loewner matrix, σL, is the Loewner matrix associatedto sH(s).
σL =
λ1v1r1−`1w1µ1
λ1−µ1· · · λ1v1rk−`1wkµk
λ1−µk...
. . ....
λqvqr1−`qw1µ1λq−µ1
· · · λqvqrk−`qwkµkλq−µk
∈ Cq×k
σL satisfiesσLM − ΛσL = LWM − ΛVR
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 23 / 30
The shifted Loewner matrix
The shifted Loewner matrix, σL, is the Loewner matrix associatedto sH(s).
σL =
λ1v1r1−`1w1µ1
λ1−µ1· · · λ1v1rk−`1wkµk
λ1−µk...
. . ....
λqvqr1−`qw1µ1λq−µ1
· · · λqvqrk−`qwkµkλq−µk
∈ Cq×k
σL satisfiesσLM − ΛσL = LWM − ΛVR
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 23 / 30
Construction of Interpolants (Models)
Assume that k = `, and let
det (xL− σL) 6= 0, x ∈ {λi} ∪ {µj}
Then
E = −L, A = −σL, B = V, C = W
is a minimal realization of an interpolant of the data, i.e., the function
H(s) = W(σL− sL)−1V
interpolates the data.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 24 / 30
Construction of Interpolants (Models)
Assume that k = `, and let
det (xL− σL) 6= 0, x ∈ {λi} ∪ {µj}
Then
E = −L, A = −σL, B = V, C = W
is a minimal realization of an interpolant of the data, i.e., the function
H(s) = W(σL− sL)−1V
interpolates the data.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 24 / 30
Construction of Interpolants (Models)
Assume that k = `, and let
det (xL− σL) 6= 0, x ∈ {λi} ∪ {µj}
Then
E = −L, A = −σL, B = V, C = W
is a minimal realization of an interpolant of the data, i.e., the function
H(s) = W(σL− sL)−1V
interpolates the data.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 24 / 30
Construction of interpolants: New procedure
Main assumption:
rank (xL− σL) = rank(
L σL)
= rank(
LσL
)=: k , x ∈ {λi} ∪ {µj}
Then for some x ∈ {λi} ∪ {µj}, we compute the SVD
xL− σL = YΣX
with rank (xL− σL) = rank (Σ) = size (Σ) =: k , Y ∈ Cν×k , X ∈ Ck×ρ.
Theorem. A realization [E,A,B,C], of an interpolant is given as follows:
E = −Y∗LX∗ B = Y∗VA = −Y∗σLX∗ C = WX∗
Remark. The system [E,A,B,C] can now be further reduced using any ofthe usual reduction methods.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 25 / 30
Construction of interpolants: New procedureMain assumption:
rank (xL− σL) = rank(
L σL)
= rank(
LσL
)=: k , x ∈ {λi} ∪ {µj}
Then for some x ∈ {λi} ∪ {µj}, we compute the SVD
xL− σL = YΣX
with rank (xL− σL) = rank (Σ) = size (Σ) =: k , Y ∈ Cν×k , X ∈ Ck×ρ.
Theorem. A realization [E,A,B,C], of an interpolant is given as follows:
E = −Y∗LX∗ B = Y∗VA = −Y∗σLX∗ C = WX∗
Remark. The system [E,A,B,C] can now be further reduced using any ofthe usual reduction methods.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 25 / 30
Construction of interpolants: New procedureMain assumption:
rank (xL− σL) = rank(
L σL)
= rank(
LσL
)=: k , x ∈ {λi} ∪ {µj}
Then for some x ∈ {λi} ∪ {µj}, we compute the SVD
xL− σL = YΣX
with rank (xL− σL) = rank (Σ) = size (Σ) =: k , Y ∈ Cν×k , X ∈ Ck×ρ.
Theorem. A realization [E,A,B,C], of an interpolant is given as follows:
E = −Y∗LX∗ B = Y∗VA = −Y∗σLX∗ C = WX∗
Remark. The system [E,A,B,C] can now be further reduced using any ofthe usual reduction methods.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 25 / 30
Construction of interpolants: New procedureMain assumption:
rank (xL− σL) = rank(
L σL)
= rank(
LσL
)=: k , x ∈ {λi} ∪ {µj}
Then for some x ∈ {λi} ∪ {µj}, we compute the SVD
xL− σL = YΣX
with rank (xL− σL) = rank (Σ) = size (Σ) =: k , Y ∈ Cν×k , X ∈ Ck×ρ.
Theorem. A realization [E,A,B,C], of an interpolant is given as follows:
E = −Y∗LX∗ B = Y∗VA = −Y∗σLX∗ C = WX∗
Remark. The system [E,A,B,C] can now be further reduced using any ofthe usual reduction methods.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 25 / 30
Example: Four-pole band-pass filter•1000 measurements between 40 and 120 GHz; S-parameters 2× 2, MIMO interpolation ⇒ L, σL ∈ R2000×2000.
0 10 20 30 40 50 60 70 80−18
−16
−14
−12
−10
−8
−6
−4
−2
0Singular values of 2 × 2 system vs 1 × 1 systems
1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2−35
−30
−25
−20
−15
−10
−5
0 Magnitude of S(1,1), S(1,2) and 21st order approximants
The singular values of L, σL The S(1, 1) and S(1, 2) parameter data
30 40 50 60 70 80 90 100 110−200
−150
−100
−50
0
50
100
150
200 Phase S(1,1) and 21st order approximant
30 40 50 60 70 80 90 100 110−130
−120
−110
−100
−90
−80
−70
−60
−50 Error: singular values of frequency response for 21st order approximant
Angle of S(1, 1) Frequency response error: data vs 21st order approximant
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 26 / 30
Comparison: Loewner method vs vector fitting
Tangential interpolation
red. order cpu time H∞ norm stabilitycoax (2× 2 S-params): 49 46 1.002 9·10−7
two lines (4× 4 S-params): 10 42 1.044 stable
Vector fitting
red. order cpu time H∞ norm stabilitycoax (2× 2 S-params): 320 34 1+tol stable
two lines (4× 4 S-params): 600 206 1+tol stable
Remark
• For tangential interpolation, the cpu time depends on the number ofsamples, not the number of ports.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 27 / 30
Comparison: Loewner method vs vector fitting
Tangential interpolation
red. order cpu time H∞ norm stabilitycoax (2× 2 S-params): 49 46 1.002 9·10−7
two lines (4× 4 S-params): 10 42 1.044 stable
Vector fitting
red. order cpu time H∞ norm stabilitycoax (2× 2 S-params): 320 34 1+tol stable
two lines (4× 4 S-params): 600 206 1+tol stable
Remark
• For tangential interpolation, the cpu time depends on the number ofsamples, not the number of ports.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 27 / 30
Comparison: Loewner method vs vector fitting
Tangential interpolation
red. order cpu time H∞ norm stabilitycoax (2× 2 S-params): 49 46 1.002 9·10−7
two lines (4× 4 S-params): 10 42 1.044 stable
Vector fitting
red. order cpu time H∞ norm stabilitycoax (2× 2 S-params): 320 34 1+tol stable
two lines (4× 4 S-params): 600 206 1+tol stable
Remark
• For tangential interpolation, the cpu time depends on the number ofsamples, not the number of ports.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 27 / 30
Summary
CNTs: suitable for new generation of interconnects.
PWGs: suitable for new generation of interconnects and for other chipcomponents.
Mixed-signal chips: Black-box approach to analog design.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 28 / 30
Summary
CNTs: suitable for new generation of interconnects.
PWGs: suitable for new generation of interconnects and for other chipcomponents.
Mixed-signal chips: Black-box approach to analog design.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 28 / 30
Summary
CNTs: suitable for new generation of interconnects.
PWGs: suitable for new generation of interconnects and for other chipcomponents.
Mixed-signal chips: Black-box approach to analog design.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 28 / 30
Summary
CNTs: suitable for new generation of interconnects.
PWGs: suitable for new generation of interconnects and for other chipcomponents.
Mixed-signal chips: Black-box approach to analog design.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 28 / 30
Some mathematical challenges
CNTs: Develop a scalable state space representation of carbonnanotube circuit models that accurately capture the statistical distributionof single as well as carbon nanotube bundles.
CNTs: Develop MOR techniques to solve and accurately approximateCNT based interconnects resulting from field solvers. Evaluate thecomplexity of MOR methods used for CNT based interconnects andconventional copper interconnects for their suitability in fast simulation.
PWGs: Develop accurate impedance based closed-form models formetallic nanoparticle dimers and plasmonic waveguides.
PWGs: For plasmonic waveguides develop nonlinear MOR techniquesfor approximation of nonplanar plasmonic waveguides.
Mixed-signal design: Apply S-parameter Loewner methods to mixedsignal chips. At the same time develop non-linear black box approachesfor the non-linear chip components.Goal: replace SPICE by higher level analog simulator.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 29 / 30
Some mathematical challenges
CNTs: Develop a scalable state space representation of carbonnanotube circuit models that accurately capture the statistical distributionof single as well as carbon nanotube bundles.
CNTs: Develop MOR techniques to solve and accurately approximateCNT based interconnects resulting from field solvers. Evaluate thecomplexity of MOR methods used for CNT based interconnects andconventional copper interconnects for their suitability in fast simulation.
PWGs: Develop accurate impedance based closed-form models formetallic nanoparticle dimers and plasmonic waveguides.
PWGs: For plasmonic waveguides develop nonlinear MOR techniquesfor approximation of nonplanar plasmonic waveguides.
Mixed-signal design: Apply S-parameter Loewner methods to mixedsignal chips. At the same time develop non-linear black box approachesfor the non-linear chip components.Goal: replace SPICE by higher level analog simulator.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 29 / 30
Some mathematical challenges
CNTs: Develop a scalable state space representation of carbonnanotube circuit models that accurately capture the statistical distributionof single as well as carbon nanotube bundles.
CNTs: Develop MOR techniques to solve and accurately approximateCNT based interconnects resulting from field solvers. Evaluate thecomplexity of MOR methods used for CNT based interconnects andconventional copper interconnects for their suitability in fast simulation.
PWGs: Develop accurate impedance based closed-form models formetallic nanoparticle dimers and plasmonic waveguides.
PWGs: For plasmonic waveguides develop nonlinear MOR techniquesfor approximation of nonplanar plasmonic waveguides.
Mixed-signal design: Apply S-parameter Loewner methods to mixedsignal chips. At the same time develop non-linear black box approachesfor the non-linear chip components.Goal: replace SPICE by higher level analog simulator.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 29 / 30
Some mathematical challenges
CNTs: Develop a scalable state space representation of carbonnanotube circuit models that accurately capture the statistical distributionof single as well as carbon nanotube bundles.
CNTs: Develop MOR techniques to solve and accurately approximateCNT based interconnects resulting from field solvers. Evaluate thecomplexity of MOR methods used for CNT based interconnects andconventional copper interconnects for their suitability in fast simulation.
PWGs: Develop accurate impedance based closed-form models formetallic nanoparticle dimers and plasmonic waveguides.
PWGs: For plasmonic waveguides develop nonlinear MOR techniquesfor approximation of nonplanar plasmonic waveguides.
Mixed-signal design: Apply S-parameter Loewner methods to mixedsignal chips. At the same time develop non-linear black box approachesfor the non-linear chip components.Goal: replace SPICE by higher level analog simulator.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 29 / 30
Some mathematical challenges
CNTs: Develop a scalable state space representation of carbonnanotube circuit models that accurately capture the statistical distributionof single as well as carbon nanotube bundles.
CNTs: Develop MOR techniques to solve and accurately approximateCNT based interconnects resulting from field solvers. Evaluate thecomplexity of MOR methods used for CNT based interconnects andconventional copper interconnects for their suitability in fast simulation.
PWGs: Develop accurate impedance based closed-form models formetallic nanoparticle dimers and plasmonic waveguides.
PWGs: For plasmonic waveguides develop nonlinear MOR techniquesfor approximation of nonplanar plasmonic waveguides.
Mixed-signal design: Apply S-parameter Loewner methods to mixedsignal chips. At the same time develop non-linear black box approachesfor the non-linear chip components.Goal: replace SPICE by higher level analog simulator.
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 29 / 30
Reference
Thanos Antoulas ( Rice U & Jacobs U ) Mathematical challenges in VLSI chip design 30 / 30