System on a Chip Technologies - Indian Statistical Institutevlsi2005/keynotes/richard_sevcik.pdf ·...

APAC: RS _January 05

System on a Chip Technologies

Rich SevcikExecutive Vice President, Xilinx

2APAC: RS _January 05

A Top-Ranking Company

Xilinx has been recognized for setting a new standard for managing a high technology business

Xilinx has been recognized for setting a new standard for managing a high technology business

Top 10 Top 10 20042004

Top 10Top 10 20032003

Top 10Top 10 20022002

Top 20Top 20 20012001

Forbes Best Managed Semiconductor Company (2004)

FORTUNE Best Companies to Work For (2001-2004)Highest ranking public company Highest ranking high-technology company


Programmability is Mainstream Logic

Source: Gartner DataquestNote: Lucent spun-off their semiconductor division in 2001 creating Agere Systems

2000

1. IBM

2. Lucent

3. LSI Logic

4. NEC

5.

2000

1. IBM

2. Lucent

3. LSI Logic

4. NEC

5.

2001

1. IBM

2. Agere

3. LSI Logic

4. NEC

5.

2001

1. IBM

2. Agere

3. LSI Logic

4. NEC

5.

2002

1. IBM

2. NEC

3. Agere

4.

2002

1. IBM

2. NEC

3. Agere

4.

1999

1. IBM

2. Lucent

3. NEC

4. LSI Logic

5. Fujitsu

6.

1999

1. IBM

2. Lucent

3. NEC

4. LSI Logic

5. Fujitsu

6.

1998

1. Lucent

2. IBM

3. NEC

4. LSI Logic

5. Fujitsu

6. Altera

7.

1998

1. Lucent

2. IBM

3. NEC

4. LSI Logic

5. Fujitsu

6. Altera

7.

2003

1. IBM

2. NEC

3.

2003

1. IBM

2. NEC

3.

ASIC/FPGA Vendor Ranking


Programmable Logic Market Share

31%33%

34%32%

31% 32% 34%

39% 32% 28% 24% 20% 18% 14%

52%

30%35% 38% 44%

50%49%

0%

20%

40%

60%

80%

100%

CY98 CY99 CY00 CY01 CY02 CY03 CY04Forecast

Xilinx Altera Other

Source: Gartner Dataquest; CY’04 – Internal Estimates

$2.3B$2.6B$4.1B$2.6B$2.1B $2.6B $3.1B


Fundamental Law ofVLSI Technology …

“The number of transistors in an integrated circuit will double every 18 months”

Today’s chips have close to 1 Billion transistors !Source: Intel web site


Moore’s Law is Alive and Well for FPGAs

100

1000

10000

100000

1000000

1985 1990 1995 2003

# of

Tra

nsis

tors

(000

s)

Intel MPUMoore's Law

TI DSP XLNX (Normalized Logic Cells)

386

486 DX

PentiumPentium Pro

Pentium III

Pentium IV Prescott

Source: Morgan Stanley, Xilinx


FPGA Design Trend Relative to ASICs Design Starts

200

300

400

500

100

2001 2002 2003 2004

ASICFPGA

Numb

er o

f Des

igns (

thou

sand

s)

Source: Gartner Group

5 4 2 1.5

500

400

100X


System On A ChipKey ‘Engineering’ Factors

• Cost

• Design cycle time / Time-To-Market

• Performance/Speed

• Density/Size

• Production volume

• Ease of fixing bugs, making changes


Slice 0

LUT Carry

LUT Carry D QCE

PRE

CLR

DQCE

PRE

CLR

Simplified FPGA ‘Slice’

• An FPGA ‘slice’ has – 2 LUTs with 4, 5 or 6 inputs– 2 registers – Carry logic for fast adders– 4 outputs, 2 registered +

2 non-registered


A Decade of Progress

• 200x More Logic– Plus memory,

µP, DSP, MGT• 40x Faster• 50x Lower Power • 500x Lower Cost

CLB CapacitySpeedPower per MHzPrice

Virtex &Virtex-E

XC4000

100x

10x

1x

Spartan-2

1000x

Virtex-II &Virtex-II Pro

Virtex-4XC4000 &Spartan

Spartan-3

'91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04

Year


Xilinx at the Forefront of Process and Wafer Technology

199919991999 200020002000 200220022002 200320032003 200420042004

90 nm90 nm

130 nm130 nm

150 nm150 nm

180 nm180 nm

200120012001

300 mm copper wafers300 mm copper wafers300 mm copper wafers200 mm wafers200 mm wafers200 mm wafers

1 Year FPGALeadership

1 Year FPGALeadership

SIASIA

XilinxXilinxXilinx

First to 150nmand 300mm

First to 90nm and 300mm

First to 130nmand 300mm


Volume

Total cost

ASIC .13µ

FPGA .13µFPGA .09µ

ASIC .09µ

ASIC Design Cost is much

higher(and increasing)!!

For each technology advance, crossover volume moves higher

FPGA vs. ASIC Cost ASIC: High volumes needed to recover design cost

ASIC cost/part is lower


The Platform FPGAMGTs I/OsMemory PowerPC

ProgrammableLogic DSP

Com

muni

catio

nPo

rt

CustomLogic

Inte

rnal

Mem

ory

Exte

rnal

Mem

ory

Port

DSP

Acce

lera

tor

µP


IP-Immersion™ TechnologyEnabled by 9-Layer Metal

Active Interconnect™Segmented Routing

Metal 1Metal 2Metal 3Metal 4

Metal 5Metal 6Metal 7Metal 8

Silicon Substrate

Poly

Advanced hard-IP block(e.g. PowerPC CPU)

Metal ‘Headroom’

Metal 9

PPC PPC


Highest Feature Performance200,000

LCs

450 MHz PowerPC with APU

>1 Gbps diff I/O with ChipSync™

10/100/1000 Ethernet MAC

500 MHz Differential Clocking

AES design security

500 MHz BRAM with FIFO & ECC

622 Mbps- 11.1 Gbps RocketIO

500 MHz XtremeDSP slice


FPGA vs. ASIC Time-To-MarketFPGA is 9 months vs. 18 months for ASIC

FPGA allows late changes, higher chance of meeting customer needs

Spec Design & verification SiliconPrototype

System Integration

SiliconProduction

FirstShip

ASIC

FirstShip

Spec Design & Verification System Integration

FPGA

50% less time


Relative Cost of ASIC BugVerify Verify Verify!!!

1 310

30

100

0

20

40

60

80

100

120

Arch Design Test System Customer

Note: Verification now takes longer than design!!


New Approach

VolumeProduction

App. TestConversion

DesignFrozen

6 to 8 weeksNONO riskNONO Engineering Resource

Up to

80%80%cost reduction

Traditional ASICConversion

Standard FPGA with Application Specific Test

Developmentwith FPGA

Time-to-Market

TimeTime--ToTo--Cost ReductionCost Reduction

EASYPATHSOLUTIONS

PrototypeBuild

BoardCertification

VolumeProduction

DesignConversion

6 to 18 months


Major Application Areas

Radio tower

Satelli te dishSatell ite

Disk array

1 2 3

4 5 67 8 9

* 8 #

SD

E SC

DL T

PRO LIAN T 80 0 0

Networking

Communication - Wireless - Wired

Automotive

Industrial

Storage, Server and Computing

Aerospace, Military, Mission Critical

Consumer Electronics

FPGAs ASICs

Examples:Mars RoverBMW Cars


Multi-Platform Offering Reduces Cost By Up To 10X

Devic

e Ca

pabil

ity &

Cos

t

Tradit ional FPGA FamilyVirtex-4

Multi-platform FPGA Family

FeatureB

FeatureA

FeatureC

FeatureB

FeatureA

FeatureD

Devicecost

Enabled by the Xilinx ASMBL™ architecture


Domain A Domain B

Domain Optimized PlatformsOne Family – Multiple Platforms

Column based features Platform A Platform B Platform x

...

Logic DomainHighest logic density

DSP DomainHighest DSP performance

Connectivity DomainEmbedded ProcessorsHigh-speed Serial I/O

Virtex-4 LX Virtex-4 SX Virtex-4 FX

Logic

Memory

DSP

Processing

High-speed I/O

Enables hard IP MixLogic, DSP, BRAM, I/O, MGT, DCM, PowerPC

Enabled by Flip-Chip PackagingI/O Columns Distributed Throughout


Both Hard & Soft IP Necessary for Programmable Systems

Programmable hard IP• Up to 10x less area• Up to 10x lower power• Up to 2x performanceCustomizable soft IP• Most flexible• Widest selection

ProtocolsPHY (ser./par.)Timing critical I/O logic & clocking

Connectivity

AlgorithmsDSP slice (MAC)DSP

PeripheralsAcceleratorsAdditional µPs

PowerPCProcessingSoftHardIP

Example: Virtex-4 FX platform FPGA


Combined with IP Solutions

Connectivity IPSource Synch Design Kits

System Generator for DSPDSP Cores/Algorithms

LogiCORE IPDesign KitsReference DesignsChipScope Pro

Third-party EDADesign ServicesSupportCustomer Education

ProcessingDomain

ConnectivityDomain

DSPDomain

Platform Studio & EDKMicroBlaze processorProcessing IP

Front-to-back design flow


Complete Design Environment

Processor Cores, IP and Silicon

Development Tools Development Boards OS Support

Breakthrough Performance At Lowest Cost


Platform Studio Design Wizards

• Extreme ease-of-use• Configure a new

platform in minutes• Minimal user-input

default system

Conceptual Mockup


Accelerate Performance Beyond the Processor Core

• Auxiliary Processing Unit (APU)

– Direct interface from CPU pipeline to FPGA logic

– Simplifies hardware accelerators

• Increase performance by over 20X


Built for Debug

• FPGA provides full internal visibility• Debug occurs at system speeds• Never too late in an FPGA

– Hardware fixed during development or after product deployment

• Enables on-chip co-verification

IO Pads

IO P

ads

IO P

ads

IO Pads

Boundary Scan TAP Controller

Embedded System Bus

MemoryArray

PPC405Core

IPCore

CustomCore

ICON

ILA

ILA

ILA

IBA CustomLogic

ILA


Processor Local Bus

405 PPC

D-Cache I-Cache

MemoryController

PowerPC Processor Block

The Ultimate Programmable System Platform

OCM Control

on-chip

mem

ory

APU Control

Auxiliary Processing

Unit


Unit

user logicuser logic

FIFO



user-definedlink

User-designed logic, interacting with the outside.Systems of interacting user logic modules.A general-purpose processor (GPP), connected to user logic.GPP can leverage speed and predictability of on-chip memory.Auxiliary processing units (APUs) enhance and accelerate GPP.APUs may access processor (e.g. its cache and registers).Multiple APUs perform different functions (e.g. I/O), concurrently.APUs can communicate using arbitrary user-defined mechanisms.Network of communicating APUs, orchestrated by the processor.

APU Control 405 PPC

D-Cache I-Cache

OCM Control

PowerPC Processor Block

MemoryController


Unit

Peripheral

Bridge

On-chi p Per. Bus


Unit

memory interface,peripherals, ...


HD-SDI Support

Connectivity ‘Standards’

NetworkingNetworkingNetworking

TelecomTelecomTelecom

ComputingComputingComputing

StorageStorageStorage

VideoVideoVideo

0.622 1.0 2.0 3.0 5.0 10.0 11.0

OC-12OC-48

GbE XAUI 10GbE

CEI (OIF)

SATA3SATA2SATA

1GFC 2GFC

PCI Express

SATA

GbE

1.45

1.25 2.5

1.5 3.0

0.6222.488

3.1251.25

6.25

1.5 3.0 6.0

1.06 2.1210GFC

6.0

10.519

SATA2

Rate (Gb/s)

CEI (OIF)

4GFC4.25

8GFC8.5

10.313

11GOBSAI

0.768-1.5 CPRI0.622 - 2.5

PCIE Gen25-6

Customer challenges• Plethora of interfacing

protocols• Differing electrical

compliance requirements• Bridging between parallel

and serial devices


Example: Virtex-4 Enables PCI Express Compliant Add-in Cards

• PCI Express requires– Support for power

management features– Spread spectrum clocking

support 64-bit, 133 MHz PCI-X

4x PCI Express


Advanced Switching Industry Rollout

’’04 04 ’’05 05 ’’0606

DesignDesign ASI 1.1 SpecificationPCI Express, SLS, SQ, SDT

Compliance Tools

Ethernet, FC, ATM & other PI’sCompliance workshops

Gen 2 PHY

WiredWirelessStorage

Converged Services

WiredWirelessStorage

Converged ServicesDeployDeploy

DevelopDevelop

Final 1.0 specFinal 1.0 specCompliance checklistCompliance checklist

11stst 4 PI’s issues4 PI’s issues

Industries 1Industries 1stst

HW demo’sHW demo’s

BFM, IP, FPGASimulation Tools

White Papers

ATCA based ASI ref designSwitches, Bridges early ‘05Software Implementations

PrePre--siliconsiliconProductProduct

AnnouncementsAnnouncements

“Advanced Switching for the PCI Express architecture”


Xilinx University Program

• Report to the CTO• Seeking to enable students• Provides donations to Universities • Manages external research partnerships


Summary

• FPGAs and ASICs are 2 complimentary approaches to SOC• Driven by Moore’s law, low design cost and shorter design

cycle time, FPGAs are becoming dominant!• ASICs remain solution of choice only for very high performance

or increasingly higher volumes

System on a Chip Technologies - Indian Statistical Institutevlsi2005/keynotes/richard_sevcik.pdf ·...

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