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Virtex-5 PCI Express Protocol Standard

Characterization Test Report

RPT064 (v1.1) December 12, 2006

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Virtex-5 PCI Express Protocol Standard www.xilinx.com RPT064 (v1.1) December 12, 2006

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Revision HistoryThe following table shows the revision history for this document. Fix

Date Version Revision

12/08/06 1.0 Initial Xilinx Confidential release.

12/12/06 1.1 Fixed typographical error in Unit Interval in Table 3, page 5. Moved section “Transmitter Return Loss,” page 25.

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Virtex-5 PCI Express Protocol Standard www.xilinx.com 3RPT064 (v1.1) December 12, 2006

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Virtex-5 PCI Express Protocol Standard

IntroductionVirtex™-5 system connectivity technology delivers the lowest power solutions for building high-speed, high-bandwidth connections between devices, boards, and boxes. The RocketIO™ GTP transceiver design and proven SelectIO™ parallel I/O technologies enable flexible bridging between emerging serial standards and existing parallel standards. The features of the Virtex-5 GTP transceivers include:

• Current Mode Logic (CML) drivers/buffers with configurable termination, voltage swing, and coupling.

• Programmable transmit pre-emphasis and receive equalization for optimal signal integrity.

• Line rates from 500 Mb/s to 3.2 Gb/s with optional 5x over-sampling to bring the low-end down to 100 Mb/s.

• Optional built-in PCS features, such as 8B/10B encoding/decoding, comma alignment, channel bonding, and clock correction.

• Fixed latency modes for minimized, deterministic datapath latency.

• Out-of-band signaling support (specifically designed to address the requirements of PCI Express® and Serial ATA protocols).

• Built-in pseudo-random bitstream (PRBS) generation/checking logic for easier bit-error rate checking.

• A configuration wizard provided in the CORE Generator™ tool and a bit error rate tester (IBERT) integrated into the ChipScope™ Pro tools for easy implementation of GTP transceiver interfaces.

This document presents the GTP transceiver electrical performance against the PCI Express specifications across process, voltage, and temperature conditions. GTP transmitter and receiver electrical characteristics were measured using a combination of lab bench setups and a High Volume Characterization (HVC) system.The methods used to characterize the transceiver are based on the standards specifications and also follow the best-practice methods for some parameters.



4 www.xilinx.com Virtex-5 PCI Express Protocol StandardRPT064 (v1.1) December 12, 2006

BackgroundR

BackgroundThe PCI Express® specification defines a packetized protocol and a load/store architecture. The specification supports copper, optical, or backplane media. The PCI Express specification uses an embedded clocking scheme. It can be used for chip-to-chip and add-in card applications to provide connectivity for adapter cards, as a graphics I/O attach point for increased graphics bandwidth, as well as an attach point to other interconnects. Some of the protocol’s key technical features include:

• Layered architecture enabling physical layer attachment to copper, optical, or emerging physical signaling media to allow for future encoding schemes.

• High bandwidth per pin for enabling unique and small form factors, reducing cost, simplifying board design and routing, and reducing signal integrity issues.

• Embedded clocking scheme enables superior frequency scalability versus source synchronous clocking.

• Bandwidth scalability with frequency and/or interconnect width.

• Low pin count, point-to-point interconnect with packetized protocol.

Lab Board Set UpAn ML523 evaluation board, with an Oztek socket hosting FF1136 package, is used to test the Virtex-5 devices. The Xilinx GUI-based XBERT platform is used for DRP loadings. A Chipscope Pro analyzer is used to configure the part. Table 1 shows the operating supply voltages and Table 2 shows the operating temperatures.

The devices chosen for characterization cover the process corner material. The number of devices varies. A minimum of two devices each were used from slow, typical, and fast process corners. The sample size is biased towards the corner silicon rather than typical and represents the worst-case behavior. The High Volume Characterization (HVC) system uses a larger sample size with five devices from each corner and 12 GTP transceivers tested per device across voltage and temperature specifications.

Table 1: Operating Supply Voltages

Condition MGTAVCC MGTAVCCPLL MGTAVTTRX MGTAVTTTX Units

VMIN 0.95 1.14V 1.14V 1.14V V

VNOM 1.0 1.20V 1.20V 1.20V V

VMAX 1.05 1.26V 1.26V 1.26V V

Notes: 1. Other FPGA voltages remain at nominal values.2. Some tests performed at VNOM ±10%.

Table 2: Operating Temperatures

ConditionTemperature

(Case for Bench Measurements)

TMAX 100°C

TROOM 25°C

TMIN –40°C




Summary of ResultsR

Summary of ResultsTable 3 summarizes the PCI Express specification requirements and the test results for the Virtex-5 GTP transceiver.

Table 3: Summary of Test Results for the PCI Express Specification

PCI Express Specifications

Virtex-5 GTPTest Results Units Compliant? Comments

Min Max Min Max

Transmitter Characteristics

Unit Interval 399.88 400.12 399.98 400.00 ps Yes

OutputDe-emphasis

–3.0 –4.0 –3.0 –4.0 dB Yes User programmable.

Median to Maximum Jitter

81.5 72.06 ps Yes Based on PCI-SIG post processing software, Sigtest.

Mean Peak-to-Peak Jitter

100 100.25 ps Yes(1) Based on PCI-SIG post processing software, Sigtest.

Rise/Fall Time 0.125 0.230 UI Yes Passes Sigtesteye mask.

Differential Return Loss

10 10 dB Yes Measured within the range of 0 to 1.25 GHz. See Figure 24.

Common Mode Return Loss


Receiver Characteristics

Differential Input Voltage

175 1200 135 mV p-p differential

Yes

Minimum Receiver Eye Width

0.4 0.3 UI Yes

Differential Return Loss


Common Mode Return Loss


Baud Rate Tolerance

–300 300 –2700 2700 ppm Yes Performed at 2.5 Gb/s.

Notes: 1. Conditional compliance. PCI-SIG electrical compliance (Sigtest) passes. See Table 11, page 20.




Receiver Electrical TestsR

Receiver Electrical Tests

Total Jitter ToleranceJitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the required sum of deterministic and random jitter and then adjusting the signal amplitude to match the driver's template shown in Figure 1. For this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter) about the mean of the zero crossing.

Jitter Tolerance MeasurementsTotal jitter tolerance measurements at 2.5 Gb/s, the PCIe required data rate, are performed to test GTP performance at 40% or greater eye closure at the receive inputs. In this measurement, both jitter components of deterministic jitter (DJ) and random jitter (RJ) are added to the input datapath. Based on channel calibration, the DJ and RJ components are fixed to introduce 0.70 UI of total jitter, and the device is tested for at least 1012 error-free bits.

DJ and RJ Components

The DJ component is generated by passing the CJPAT test pattern through 30 inches of Tyco FR4 backplane with two HMZd backplane connectors plus 15 inches of Xilinx standard FR4 trace board. CJPAT was used in this test because it is a more strenuous specification test than the compliance test pattern. The RJ component from the NoiseCom random noise source is added to the pattern generator clock source using a power splitter. With these two jitter sources in place, the jitter decomposition measurement is made using the Agilent DCA-J scope, as shown in Figure 2. To compute the total jitter in this measurement at 10–12 BER, the scope math function multiplies the RJ rms value by 14 and adds it to the DJ value. Because the Tyco 30-inch backplane plus 15 inches of Xilinx trace board introduces about 0.40 UI of DJ, the random noise source is calibrated to add another 0.30 UI of peak-to-peak RJ for a total of 0.70 UI of DJ + RJ components.

Figure 1: RX Eye Diagram

VRX-DIFF = 0mV(D+ D– Crossing Point)

VRX-DIFFp=p-MIN > 175mV

VRX-DIFF = 0mV(D+ D– Crossing Point)

0.4 UI = TRX-EYE-MIN

rpt064_01_120106





Figure 2: Jitter Decomposition at 2.5 Gb/s over a 30-Inch Tyco Backplane plus a 15-Inch Trace

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Figure 3 shows the passing input eye at 2.5 Gb/s with REFCLK = 100 MHz.

Figure 3: Passing Input Eye at 2.5 Gb/s (REFCLK = 100 MHz)

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Test Setup - Jitter Tolerance

Jitter tolerance measurements at a 2.5 Gb/s PCIe data rate using a backplane and external random noise source are performed using the test setup as shown in Figure 4. The sinusoidal modulation is turned off in this case.

Figure 4: PCIe Jitter Tolerance Setup with Media

Main Signal

NC 6108 Noise Generator

Noise Out

3325B ModulatorSync Out

Sync In

10 MHz Ref In

FM Input

IEEE

IEEE

IEEE

IEEE

83752A Sweeper

10 MHz Ref In RF Output5 dbm

Power Divider

Channel 170820A MTA

10 MHz Ref Out Channel 2

Clk InError Detector

86100C InfiniumDCA-J Scope

LX50TML523

81130A Pattern Generator

81134APulse

Generator

Data In

Clk Out

Clk Out Bar

86130A BitalyzerPattern Generator

30 in. Tyco BackplanePlus 2 Connectors

Clk In

Data P

Data N

RXP RXN

TXN

TXP Channel 2

External Trigger

Channel 1

Channel 1CLK Out 2.5 Gb/s

Divide by 25Trigger Out100 MHz

10 MHz Ref In

Clk P Clk N

CLK/REF Input

Trigger Out

REFCLK

Blue denotes back panel connection.Black denotes front panel connection.

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- PCIe test @ 2.5 Gb/s- REFCLK @ 100 MHz- Data out of BERT is CJPAT- 30 inch Tyco Backplane plus 15 inch FR4 Trace between BERT and part- 500 mV Data Out of BERT- Trigger Out Divide by 25- RX Equalization on = 11

71501C Jitter Analysis System

15 in. FR4Trace Board





Test Details - Jitter Tolerance

With fixed DJ and RJ components in place, the device is tested for at least 1012 error-free bits for each GTP corner condition tested. At a 2.5 Gb/s data rate, the minimum 6.7 minutes of error-free operation is required to test for 1012 bits. The device is tested for 15 minutes for each GTP test corner case as shown on the following screen shot.

Test Results - Jitter Tolerance

Table 4 shows the minimum tolerance results. These results were based on a data rate of 2.5 Gb/s, REFCLK = 100 MHz, fVCO = 1.25 Gb/s, RX_EQ = 11, a CJPAT pattern, and a Tyco 30-inch backplane with 15-inch FR4 trace board. The DJ is 0.4 UI, and the RJ is 0.3 UI. Each test corner is tested for 15 minutes of error-free operation. The decomposed DJ and RJ values are added for total jitter tolerance results. Tests were performed across process, voltage, and temperature using two parts each of SS, TT, and FF process corners. Six devices were tested, two each from slow, typical, and fast process corners across temperature and voltage. The eye closure that the GTP receivers encountered was 0.1 UI more than required by the PCI Express specification. GTP receivers passed the BER requirement of 10-12 under all conditions tested.

Figure 5: PCIe Testing Screen

rpt064_05_120106





Receiver Baud Rate Tolerance Test ResultsWith a PCI Express® endpoint configuration and MGTCLK (REFCLK) fixed at 100 MHz, the BERT data generator driving the Virtex-5 RX device is set to a nominal data rate of 2.5 Gb/s. The data rate is offset ± from its nominal frequency until bit error rate failure is observed, and then the ppm offset at the failure point is recorded as a “% offset value.”

First, the test is started with the passing bit error rate with a fixed 100 MHz MGTCLK and 2.5 Gb/s data generator/analyzer. The offset value is increased at the BERT data generator until the BER test fails. The last passing value is then recorded. Two sweeps are done for each run, 2.5 Gb/s + offset and 2.5 Gb/s – offset.

Data is based on default symmetric ppm offsets in the ± direction. The test was done on five Virtex-5 XC5VLX50T devices at –40°C, 0°C, and 100°C with VCC ±5% and ±10%. The results are shown in Figure 6 and summarized in Table 5. See the Virtex-5 RocketIO GTP Transceiver User Guide for attribute settings to skew the ppm offset in one direction.

For Reference: 0.27% frequency offset = 2700 ppm and CDR second-order loop filter = ON.

The GTP receiver PPM offset test was performed using the high volume testing environment. With the second order enabled, the CDR offset was recorded at 2700 ppm, well above the requirements of PCI Express.

Table 4: Total Jitter Tolerance Test Conditions and Results at 2.5 Gb/s

DeviceMGTAVCC

(V)MGTAVCCPLL

(V)MGTAVTTTX

(V)MGTAVTTRX

(V)Temperature

(°C)Total Jitter

(UI)

Typ-1

0.9 1.08 1.08 1.08 100 0.7

1 1.2 1.2 1.2 25 0.7

1.1 1.32 1.32 1.32 -40 0.7

Typ-2

0.9 1.08 1.08 1.08 100 0.7

1 1.2 1.2 1.2 25 0.7

1.1 1.32 1.32 1.32 -40 0.7

SS-1

0.9 1.08 1.08 1.08 100 0.7

1 1.2 1.2 1.2 25 0.7

1.1 1.32 1.32 1.32 -40 0.7

SS-2

0.9 1.08 1.08 1.08 100 0.7

1 1.2 1.2 1.2 25 0.7

1.1 1.32 1.32 1.32 -40 0.7

FF-1

0.9 1.08 1.08 1.08 100 0.7

1 1.2 1.2 1.2 25 0.7

1.1 1.32 1.32 1.32 -40 0.7

FF-2

0.9 1.08 1.08 1.08 100 0.7

1 1.2 1.2 1.2 25 0.7

1.1 1.32 1.32 1.32 -40 0.7





Receiver Input SensitivityThis section describes the receiver input sensitivity test for various data rates including PCI Express. Measurements are made using the High Volume test environment.

Test Setup

A variable input voltage is applied to the DUT RX from the Agilent ParBERT pattern generator, and a BER test is performed. RX input sensitivity is defined as the last passing voltage where the error detector starts to see errors.

Operating Conditions, Configurations, and Setup

Table 6 shows configurations of the TX and RX blocks.

Figure 6: Receiver PPM CDR Offset Test Results

250

200

150

100

50

0

-1.0

0-0

.92-0

.84-0

.76-0

.68-0

.60-0

.52-0

.44-0

.36-0

.28-0

.20-0

.12-0

.040.

040.

120.

200.

280.

360.

440.

520.

600.

680.

760.

840.

921.

00

CDR Offset (%)

Upper Limit

Num

ber

of G

TP

Tra

nsce

iver

s Fa

iled

Lower Limit

rpt064_06_120106

Table 5: Receiver Baud Rate Test

Reference Clock

Input Baud RateComments

Min Max

100 MHz 2.5 GHz – 300 ppm 2.5 GHz – 300 ppm ±2700 ppm at 2.5 Gb/s

Table 6: GTP Transceiver Block Configurations

TX Block Mode/Configuration RX Block Mode/Configuration

Logic Interface 10 bits Logic Interface 10 bits

8B/10B Encode Disabled 8B/10B Encode Disabled

Internal DATAWIDTH 10 bits Internal DATAWIDTH 10 bits





Equipment Setup

The HVC system is used to collect the data. Table 7 lists the setup parameters for the pattern generator and the analyzer. A PRBS31 pattern is used to measure the input sensitivity. From the point of view of PCI Express specifications, this represents a tougher test pattern on the receiver than the 8B/10B encoded data patterns.

Board Setup and Clock Connections

The Virtex-5 FF1136 HVC test fixture provides connections from the HVC to the DUT.

Receiver Input Sensitivity Specifications

The characterization data for the receiver input sensitivity is summarized in Table 8. The histogram shown in Figure 7 is summarized in Table 9. The input sensitivity measurement results indicate that the GTP transceivers tested, based on the conditions listed, pass the PCI Express requirements.

Table 7: HVC ParBERT Setup

Pattern Generator Setup

Value Analyzer Setup Value

Output LevelSTART = 400 mV, STOP = 0 mV, STEP = 15 mV

Test Length 0.5s

Pattern PRBS31 Pattern PRBS31

Data Rate 2.500 Gb/s Data Rate 2.500 Gb/s

Table 8: Receiver Input Sensitivity Test Details

Test Type Description

Test Case RX sensitivity, differential peak-peak, in mV

Test Conditions VCC = NOM, ±5%, Temperature = –40°C to 100°C (I-Grade)

Method RX input voltage is programmed from 400 mV to 0 mV in 15 mV steps, until the error detector sees an error.

Data Rates Tested 2.5 Gb/s

Pattern PRBS31

Results (2.5 Gb/s) Average = 75 mV, Standard Deviation = 18 mV, Average+3.5σ = 137 mV

Observation Reported value is differential (peak-peak)





Receiver Return LossReceiver input impedance can result in a differential return loss better than 10 dB and a common mode return loss better than 6 dB from 50 MHz to 1.25 GHz. This includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is 100Ω for differential return loss and 25Ω for common mode. The frequency domain return loss measurements (Figure 8 and Figure 9) were made using the UNH interoperability lab guidelines. The four traces represent different GTP receivers with varying PCB trace lengths. The return loss measurements based on the UNH Interoperability Labs testing show that the differential and common mode return loss are within the requirements of the PCI Express specifications.

Figure 7: Receiver Sensitivity

Table 9: Receiver Sensitivity Summary

Min Max Mean Median Standard Deviation Units

45 135 78 75 18 mV

900

800

700

500

600

400

300

200

100

0

0 15 30 45 60 75

Rx Sensitivity (mV Differential)

Dat

apoi

nts

90 105 135 165 195120 150 180 210

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Figure 8: SDD11 (RX Differential Return Loss) vs. Frequency

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Transmitter Electrical TestsR

Transmitter Electrical TestsVirtex-5 GTP transmitters were tested for jitter, output voltage, and rise and fall times based on the compliance test recommendations by the PCI-SIG. http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library/

Pre-emphasis and return loss measurements were bench tested.

Transmitter Test Setup

Methodology

Xilinx ML523 Evaluation board with Oztek socket hosting FF1136 package is used to test the devices. Xilinx GUI based XBERT platform is used for DRP loadings. Xilinx Chipscope is used to configure the device.

• Analysis Equipment and software: For transmitter, jitter analysis, the post capture jitter analysis software Sigtest v2.1 was used along with a high bandwidth Tektronix TDS6154C Digital Storage Oscilloscope (15 GHz, 40 GS/s).

• Compliance Load Board: Intel's Signal Quality Load Board or PCI Express Compliance Load Board (CLB) was plugged into the adapter card as required by the

Figure 9: SCC11 (RX Common Mode Return Loss) vs. Frequency

rpt064_09_120106


http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library/




PCI-SIG. The card under test must be plugged into the PCIe slot in the Compliance Load Board.

• Characterization boards: The ML523 was used to measure across process, voltage, and temperature corners. The ML523 does not have a PCIe connector an SMA-to-PCIe adapter card was used to provide connectivity to the Compliance Load board. The test setup is shown in Figure 12. The test conditions are worse than what would normally be observed. The user card normally is plugged directly into the Compliance Load Board resulting in lower high-frequency losses.

• Noise Generation: Internal noise generators were used in the FPGA logic to emulate realistic design situations. The flip-flops were toggling at a 75 MHz clock frequency. The 75 MHz clock is generated using a Stanford Research Systems, Model CG635, 2.05 GHz Synthesized Clock Generator.

• Temperature control: Thermonics T-2820 Precision Temperature Forcing System was used to force temperature on the DUT.

• Reference clock: A 100 MHz clock provided by the Compliance Load Board is the reference clock for GTP transmitter testing.

• Data Generation: A PCI Express compliance pattern generated in the FPGA logic and transmitted through the configured GTP transceiver.

Figure 10: PCI Express Compliance Load Board

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Figure 11: ML523 with Adaptor Card

Figure 12: PCI Express Transmitter Test Setup

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Test Conditions - Transmitter

The tests were performed at 0°C, 25°C, and 100°C at nominal and VCC (±10%) values (Table 10.) Other FPGA voltages remain at nominal values.

Test Details - Transmitter

A total of 10 devices were tested for TX characteristics. Four devices each from SS and FF process corners along with two TT devices were used for characterization. The sample size is biased towards the corner silicon rather than typical and represents the worst-case behavior.

Test Results - Transmitter

Sigtest measurements across process, voltage, and temperature conditions show that the GTP transmitter passes compliance in all but two cases (SS corner, –10% VCC at 0°C). The failed test was due to the output level which can be adjusted with output voltage control settings. These failures went away with the default PCIe settings, when they were re-measured a –5% VCC, the actual device specification. Figure 13 shows the eye diagrams from Sigtest post processing (transition and non-transition). Figure 14 shows a snapshot of a portion of Sigtest output. The summary of results from a total of 98 data points is shown in Table 11.

Table 10: Operating Supply Voltages

Condition MGTAVCC

VMIN 0.9V

VNOM 1.0V

VMAX 1.1V

Figure 13: Transition and Non-Transition Eye from Sigtest Post Processing

rpt064_13_120106





Figure 14: Snapshot of Sigtest Output

rpt064_14_120106

Table 11: Summary of TX PCI Express Parameters

Median MeanStandard Deviation

Minimum Value

Maximum Value

Specification Units

Mean Unit Interval 399.9950125 399.9950329 0.00036983 399.994112 399.995809 399.88 - 402.12 ps

Maximum Unit Interval 399.997665 399.9978111 0.000951312 399.996109 400.000595 ps

Minimum Unit Interval 399.992355 399.9922937 0.000901083 399.989517 399.994461 ps

Minimum Time Between Crossovers

375.7778885 374.9303117 4.428820997 361.244166 392.501645 0 ps

Per Edge RMS Jitter 11.9985595 12.7187757 2.431455917 7.83277 18.447128 ps

Mean Median-to-Peak Jitter 32.598163 38.03047863 11.62909658 24.474583 72.062961 81.5 ps

Maximum Median-to-Peak Jitter

46.949221 50.58819727 12.51226415 26.646109 80.504303 ps

Minimum Median-to-Peak Jitter

24.879358 29.45003134 10.66264952 17.479057 63.876014 ps

Mean Peak-to-Peak Jitter 59.2783375 64.03212714 14.49694677 34.476431 100.252403 100 ps

Maximum Peak-to-Peak Jitter

76.8815715 81.25133597 15.98268201 38.036513 125.982215 ps

Minimum Peak-to-Peak Jitter

46.3525605 51.23063203 13.84597561 32.154618 86.606367 ps





Histograms of Tests

Minimum Transition Eye Voltage

–0.54206 –0.544833878 0.022986072 –0.59036 –0.46992 –0.400 V

Maximum Transition Eye Voltage

0.52192 0.523919184 0.023657303 0.47216 0.58816 0.600 V

Minimum Non-Transition Eye Voltage

–0.5368 –0.543130204 0.023821219 –0.59036 –0.45968 –0.400 V

Maximum Non-Transition Eye Voltage

0.49614 0.503190612 0.029500651 0.44912 0.5854 0.600 V

Minimum Transition Eye Voltage Margin Above Eye

0.130624 0.131473531 0.019757328 0.093386 0.179177 V

Minimum Transition Eye Voltage Margin Below Eye

–0.1127405 –0.111685612 0.018266168 –0.184608 –0.070881 V

Minimum Non-Transition Eye Voltage Margin Above Eye

0.137147 0.1127735 0.053108953 0.000708 0.164638 V

Minimum Non Transition Eye Voltage Margin Below Eye

–0.12517 –0.101009337 0.051169426 –0.149586 0.017376 V

Data Rate 2.500031 2.500031041 2.38084e6 2.500026 2.500037 Gb/s

Table 11: Summary of TX PCI Express Parameters (Continued)

Median MeanStandard Deviation

Minimum Value

Maximum Value

Specification Units

Figure 15: Distribution of Mean Unit Interval

25

20

15

10

5

0

399.

9941

12

399.

9943

006

399.

9944

891

399.

9946

777

399.

9948

662

399.

9950

548

UI (ps)

Cou

nt

399.

9952

433

399.

9954

319

399.

9956

204

Mor

e

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Figure 16: Distribution of Minimum Time Between Crossovers

Figure 17: Distribution of Per-Edge RMS Jitter

Figure 18: Distribution of Mean Median-to-Peak Jitter

50

40

30

20

10

45

35

25

15

50

350 355 360 365 370 375 380

Time (ps)

Cou

nt385 390 395 400 More

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40

30

20

10

35

25

15

5

0

0 2 4 86 10 12 14 16

Time (ps)

Cou

nt

18 20 22 24 26 28 30 32 More

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35

30

20

10

25

15

5

0

10 15 20 3025 35 40 45 50

Time (ps)

Cou

nt

55 60 65 70 75 80 85 90 More

rpt064_18_120106





Figure 19: Distribution of Mean Peak-to-Peak Jitter

Figure 20: Distribution of Minimum Transition Eye Voltage

Figure 21: Distribution of Maximum Transition Eye Voltage

40

35

30

20

10

25

15

5

0

10 20 30 5040 60 70 80 90

Time (ps)

Cou

nt100 110 120 130 140 150 More

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50

4540

25

10

15

30

35

20

50

-0.7

-0.6

75-0

.65

-0.6

-0.6

25

-0.5

75-0

.55

-0.5

25 -0.5

Volts

Cou

nt

-0.4

75-0

.45

-0.4

25 -0.4

-0.3

75-0

.35

Mor

e

rpt064_20_120106

50

4540

25

10

15

30

35

20

50

0.35

0.37

50.

40.

450.

425

0.47

50.

50.

525

0.55

Volts

Cou

nt

0.57

50.

60.

625

0.65

0.67

50.

7M

ore

rpt064_21_120106





Figure 22: Distribution of Minimum Non-Transition Eye Voltage

Figure 23: Distribution of Maximum Non-Transition Eye Voltage

45

40

25

10

15

30

35

20

5

0

-0.7

-0.6

75-0

.65

-0.6

-0.6

25

-0.5

75-0

.55

-0.5

25 -0.5

Volts

Cou

nt

-0.4

75-0

.45

-0.4

25 -0.4

-0.3

75-0

.35

Mor

e

rpt064_22_120106

40

25

10

15

30

35

20

5

0

0.35

0.37

50.

40.

450.

425

0.47

50.

50.

525

0.55

Volts

Cou

nt

0.57

50.

60.

625

0.65

0.67

50.

7M

ore

rpt064_23_120106





Transmitter Return LossThe frequency domain return loss measurements (Figure 24 and Figure 25) were made using the UNH interoperability lab guidelines. The four traces represent different GTP receivers with varying PCB trace lengths. The return loss measurements based on the UNH Interoperability Labs testing show that the differential and common mode return loss are within the requirements of the PCI Express specifications.

Figure 24: TX Differential Return Loss vs. Frequency

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Transmitter Rise and Fall Times Test ResultsThe GTP TX output rise and fall time measurements are made as a function of the MGTAVTTTX voltage supply. In these tests, the data rate is 2.5 Gb/s, REFCLK = 250 MHz, and the operating temperature was –40°C, 0°C, and 100°C. The resulting trends are plotted in the data plots shown in the following figures.

Figure 26 and Figure 27 show the histogram distribution of the rise time of the XCV5LX50T TX side output at a 2.5 Gb/s data rate, with a 00001111 data pattern, and MGTAVTTTX equal to 1.2V ± 5%. Table 12 summarizes the transmitter rise time.

Figure 25: TX Common Mode Return Loss vs. Frequency

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Figure 28 and Figure 29 show the histogram distribution of the fall time of the XCV5LX50T TX side output at a 2.5 Gb/s data rate, with a 00001111 data pattern, and MGTAVTTTX equal to 1.2V + 5%. Table 13 summarizes the transmitter fall time.

Figure 26: XCV5LX50T Rise Time at MGTAVTTTX = 1.26V

Figure 27: XCV5LX50T Rise Time at MGTAVTTTX = 1.14V

Table 12: Transmitter Rise Time Summary


92 162 126 127 9.43 ps

60

50

40

20

30

10

0

RT AVTTTX=1.2V+5%

Rise Time (ps)

Num

ber

of G

TP

Tra

nsce

iver

s

rpt064_26_121206

40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 165 176

60

50

40

20

30

10

040 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 165 176

RT AVTTTX=1.2V-5%

Rise Time (ps)

Num

ber

of G

TP

Tra

nsce

iver

s

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Transmit Pre-Emphasis TestTo verify the pre-emphasis (de-emphasis) control and to measure the amplitude and the output jitter generation, the GTP transceiver was placed in fabric loopback mode with the data pattern (alternating 000111) generated by the signal generator of the Agilent BERT. TXPREEMPHASIS [2:0] was swept through the various settings and the near-end output amplitude (Min and Max) was measured using the Agilent DCA. The definition of Min and Max is shown in Figure 30.

Figure 28: XCV5LX50T Fall Time at MGTAVTTTX = 1.26V

Figure 29: XCV5LX50T Fall Time at MGTAVTTTX = 1.14V

Table 13: Transmitter Fall Time Summary


70 148 105 105 12.29 ps

30

25

20

10

15

5

0

FT AVTTTX=1.2V+5%

Fall Time (ps)

Num

ber

of G

TP

Tra

nsce

iver

s

rpt064_28_121206

40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 165 176

30

25

20

10

15

5

0

FT AVTTTX=1.2V-5%

Fall Time (ps)

Num

ber

of G

TP

Tra

nsce

iver

s

rpt064_29_121206

40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 165 176





Characterization Data Plot

Figure 31 shows the XCV5LX50T transmitter pre-emphasis trend at a 2.5 Gb/s data rate with a 00001111 data pattern. As shown in this figure, the transmitter pre-emphasis ratio with TXPREEMPHASIS equal to 111 and TXDIFFCTRL [2:0] (= TXBUFDIFFCTRL [2:0]) equal to 101 is between -3 dB to -4 dB, which meets the PCIe pre-emphasis specifications.

Figure 30: Conceptual Diagram Showing the Min and Max Voltage Due to Pre-Emphasis

Min Max

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Figure 31: XCV5LX50 Transmitter Pre-Emphasis Trend

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-4.0

-3.5

-4.5

0 1 2 3 4 5 6 7

TX Pre-Emphasis

DD

OU

T(d

B)

rpt064_31_121206

120A

120B

122A

122B

120A

120B

122A

122B

120A

120B

122A

122B

120A

120B

122A

122B

120A

120B

122A

122B

120A

120B

122A





Qualitative View of Pre-Emphasis Control

Figure 32 shows a scope capture plot for various TX output waveforms corresponding to various pre-emphasis settings.

The qualitative eye opening impact of the pre-emphasis on the far-end eye was also captured. The test pattern was transmitted over 40 inches of FR4 trace board at 2.5 Gb/s and 3.125 Gb/s, and eye-opening plots are captured at the near and far end of the 40-inch FR4 link. A significant reduction in the far-end jitter is observed, as shown in Figure 33.

Figure 32: TX Output Waveform for Different Pre-Emphasis Settings

Figure 33: Impact of No Pre-Emphasis vs. Max Pre-Emphasis on the Far-End Jitter at 2.5 Gb/s

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Virtex-5 PCI Express Protocol Standard - BDTIC · 2012-11-20 · Virtex-5 PCI Express Protocol...

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Transcript of Virtex-5 PCI Express Protocol Standard - BDTIC · 2012-11-20 · Virtex-5 PCI Express Protocol...