Lab 4 PreviewLab 4 Preview

Friday, 18 AugustFriday, 18 August

SEQUENTIAL SEQUENTIAL CIRCUITSCIRCUITS

Design Using Flip-Design Using Flip-flopsflops

Review of Digital IReview of Digital I

Sequential Circuit Sequential Circuit BehaviourBehaviour

• Is determined from the inputs, Is determined from the inputs, outputs and present state.outputs and present state.

• The outputs and the next state are a The outputs and the next state are a function of the inputs and the function of the inputs and the present state.present state.

Synchronous Sequential Synchronous Sequential CircuitCircuit

• Includes flip-flops with the clock inputs Includes flip-flops with the clock inputs driven directly or indirectly by a clock driven directly or indirectly by a clock signal.signal.– Flip-flops – may be of any type.Flip-flops – may be of any type.

• The direct sets and resets are unused The direct sets and resets are unused during normal circuit functionabiity.during normal circuit functionabiity.

• Logic diagram – may or may not include Logic diagram – may or may not include combinational gates. combinational gates.

Example Example Using J-K Flip-flopUsing J-K Flip-flop

Example: J-K Flip-flop Example: J-K Flip-flop DesignDesign

Input equationsInput equations

• Flip-flop input equationFlip-flop input equation

JJAA = ( XB +NY.C ) = ( XB +NY.C )

KKAA = ( Y.NB + C ) = ( Y.NB + C )

• JJAA and K and KAA : Boolean variables : Boolean variables– J and K – inputs of a JK flip-flop.J and K – inputs of a JK flip-flop.– Subscript A – name of flip-flop output.Subscript A – name of flip-flop output.– C – clock input.C – clock input.– X, B and Y – inputs to combinational circuit.X, B and Y – inputs to combinational circuit.

Example Example Using D-Flip-flopUsing D-Flip-flop

The Flip-flop Input The Flip-flop Input EquationsEquations

DDAA = (AX +BX) Equations for FF = (AX +BX) Equations for FF inputsinputs

DDBB = NA.X = NA.X

Y = ( A+B ) . NXY = ( A+B ) . NX -- Equation for output Y Equation for output Y

– Subscripts A and B – names of FF Subscripts A and B – names of FF outputs.outputs.

Example 2: D Flip-flop Example 2: D Flip-flop DesignDesign

State table for Circuit of State table for Circuit of Fig 4.18Fig 4.18

Two-Dimensional State Two-Dimensional State Table for the Circuit in Table for the Circuit in

Figure 4.18Figure 4.18

Example Example Using D-Flip-flopUsing D-Flip-flop

Logic Diagram and State Logic Diagram and State Table for DTable for DAA

Example Example Using J-K Flip-flopUsing J-K Flip-flop

State Table for Circuit with State Table for Circuit with JK Flip-FlopsJK Flip-Flops

State DiagramState Diagram

Fig 4.21 Construction of a Fig 4.21 Construction of a State DiagramState Diagram

Table 4.5 State Table for Table 4.5 State Table for State Diagram in Fig 4.21State Diagram in Fig 4.21

BCD to Excess-3 BCD to Excess-3 DecoderDecoderExample Example

Sequence Tables for BCD to Sequence Tables for BCD to Excess-3 Code Converter Excess-3 Code Converter

ExampleExample

Construction of a State Construction of a State DiagramDiagram

Table 4.5 with names Table 4.5 with names Replaced by Binary CodesReplaced by Binary Codes

Design Example 1 Design Example 1 Using D-Flip-flopUsing D-Flip-flop

State Table for Design State Table for Design ExampleExample

Flip-Flop Characteristic Flip-Flop Characteristic TableTable

Flip-Flop Excitation Flip-Flop Excitation TablesTables

State Diagram for Design State Diagram for Design ExampleExample

Maps for Input Equations Maps for Input Equations and Output Yand Output Y

Logic Diagram for Sequential Logic Diagram for Sequential Circuit with D Flip-FlopsCircuit with D Flip-Flops

Design Example 2Design Example 2Using D-Flip-flopUsing D-Flip-flop

State table for Second State table for Second Design ExampleDesign Example

Maps for Simplifying Input Maps for Simplifying Input EquationsEquations

Design Using D Flip-flopsDesign Using D Flip-flops

Flip-Flop Characteristic TableFlip-Flop Characteristic Table

Flip-Flop Excitation TablesFlip-Flop Excitation Tables

Design Procedure using JK Flip-Design Procedure using JK Flip-Flops Flops

Maps for J and K Input Maps for J and K Input EquationsEquations

Fig 4.28 Logic Diagram for Fig 4.28 Logic Diagram for Sequential Circuit with JK Flip-flopsSequential Circuit with JK Flip-flops

Logic Simulation Verification for the Logic Simulation Verification for the Circuit in Fig 4.28Circuit in Fig 4.28

Lab 4 : OverviewLab 4 : Overview

Synchronous Up/down Synchronous Up/down counter counter

ObjectiveObjective

• To design a 3 bit up/down To design a 3 bit up/down synchronous countersynchronous counter

• Your are required to Submit :Your are required to Submit :• Printed Schematic Diagram and Printed Schematic Diagram and

waveformwaveform• Truth TableTruth Table• K-Map & Boolean ExpressionK-Map & Boolean Expression

SimulationSimulation

• For simulation, Input your clock manuallyFor simulation, Input your clock manually

Upload Design to UP2 Upload Design to UP2 BoardBoard

• Once simulation is successful, then Once simulation is successful, then upload your design on your up2 boardupload your design on your up2 board

• For clock input use the 1Hz clock output For clock input use the 1Hz clock output from function generatorfrom function generator– use flex expansion slotuse flex expansion slot

PIN 91

Upload….contUpload….cont

• Output from each FF is connected to Output from each FF is connected to 7447 BCD to 7seg decoder to display 7447 BCD to 7seg decoder to display its output to the 7seg display.its output to the 7seg display.

Your design of Up/down

counter

7447BCD to

7Seg a - g

Pin Configuration to output(use flex digit 1 or 2 )

gnd

f = 1/t = 1hzThereforeT = 1/1 = 1sec

The TwistThe Twist• We have decided to predefine the counters We have decided to predefine the counters

according to group:according to group:• Group 1 : 1>3>4>5>7>1>7>5>4>3>1……. (rp=1)Group 1 : 1>3>4>5>7>1>7>5>4>3>1……. (rp=1)• Group 2 : 2>4>5>6>7>2>7>6>5>4>2……. (rp=2)Group 2 : 2>4>5>6>7>2>7>6>5>4>2……. (rp=2)• Group 3 : 3>4>5>6>7>3>7>6>5>4>3……. (rp=3)Group 3 : 3>4>5>6>7>3>7>6>5>4>3……. (rp=3)• Group 4 : 1>3>5>6>7>1>7>6>5>3>1……. (rp=1)Group 4 : 1>3>5>6>7>1>7>6>5>3>1……. (rp=1)• Group 5 : 2>3>4>5>7>2>7>5>4>3>2……. (rp=2)Group 5 : 2>3>4>5>7>2>7>5>4>3>2……. (rp=2)• Group 6 : 1>2>3>6>7>1>7>6>3>2>1……. (rp=1)Group 6 : 1>2>3>6>7>1>7>6>3>2>1……. (rp=1)• Group (Add) : 0>1>3>5>7>0>7>5>3>1>0…..Group (Add) : 0>1>3>5>7>0>7>5>3>1>0…..

(rp=0)(rp=0)• Please use Please use JK Flip-FlopsJK Flip-Flops for your design for your design

Additional ReadingAdditional Reading

• Johnson CounterJohnson Counter• Ring CounterRing Counter• The differences and its schematic The differences and its schematic

diagram (4 bits)diagram (4 bits)

Thank YouThank You