ECE 301 – Digital Electronics Flip-Flops and Registers (Lecture #15)

ECE 301 – Digital Electronics

Flip-Flops and Registers

(Lecture #15)

ECE 301 - Digital Electronics 2

Basic Memory Elements

Basic Memory Elements Basic Latch

A feedback connection of two NOR gates or two NAND gates, which can store one bit of information.

Can be set to 1 or reset to 0.

Gated Latch A basic latch that also includes input gating and a

control input signal (i.e. the clock).

Flip-Flop A storage element based on the gated latch principle,

which can have its output state changed only on the edge of the controlling clock signal.

D Flip-Flop

Master-Slave Flip-Flop

D Flip-Flop

D Flip-Flop: Master-Slave

Master active

Slave active

Positive Edge-triggered Flip-Flop

D Flip-Flop

D Flip-Flop: Edge-Triggered

positive edge

negative edge

D Flip-Flop: Symbols

D Flip-Flop: Function Table

Comparison of Level-Sensitive and Edge-Triggered

Memory Elements

Basic Memory Elements

(b) Timing diagram

Clock Q a

(a) Circuit

Gated D Latch

Positive Edge-triggered D Flip-Flop

Negative Edge-triggered D Flip-Flop

+ Edge-triggered D FF

Gated D Latch

- Edge-triggered D FF

Note that the Latch, Positive Edge-triggered FF,

and Negative Edge-triggered FF each have a unique symbol

Asynchronous Preset and Clear Signals

Flip-Flops

(a) Circuit

Preset

(b) Graphical symbol

Presetmaster slave

Asynchronous Preset and Clear

JK Flip-Flop

Flip-Flops

JK Flip-Flop

T Flip-Flop

Flip-Flops

T Flip-Flop

Registers

Registers Register

Consists of N Flip-Flops Stores N bits Common clock used for all Flip-Flops

Shift Register A register that provides the ability to shift its

contents (either left or right). Must use Flip-Flops

Either edge-triggered or master-slave Cannot use Level-sensitive Gated Latches

4-bit Register

Registers

4-bit Register with Parallel Load

Registers

2-to-1 Multiplexer

4-bit Serial-In Serial-OutShift Register

Registers

4-bit SI/SO Shift Register

common clock Edge-triggeredFlip-Flop

Parallel-In Parallel-OutShift Register

Registers

Q 3 Q 2 Q 1 Q 0

ClockParallel input

Parallel output

Shift/LoadSerialinput

Q2-to-1

Multiplexer

Parallel-In Parallel-OutBi-directional Shift Register

Registers

4-bit PI/PO Bi-directionalShift Register

Acknowledgments

The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for

Digital Design (4th Edition).

They are the property of and are copyrighted by Pearson Education.

ECE 301 – Digital Electronics Flip-Flops and Registers (Lecture #15)

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