Sequential Logic (2) Multivibrator Circuits

1

Digital Integrated Circuits © Prentice Hall 2000Sequential Logic

EECS 141 – S02Lecture 17

Sequential Logic (2)Multivibrator Circuits


Last Lecture

l Dynamic Circuits Wrap-up» Differential Domino

» np-CMOS

» Logic Style Summary

l Introduction to Sequential Logic» Latch vs. Flip-flop

» RS, Mux-based latch

» Master-slave flip-flop

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Today’s Lecture

l Sequential Logic (Cont’d)» Timing Definitions

» Pulse-triggered latches

» C2MOS latch

» TSPC logic

l Multi-vibrator Circuits» Schmitt Trigger

» Monostable

» Astable (Oscillator)


2-phase dynamic flip-flop

φ2φ1

DIn

Input Sampled

Output Enable

φ1

φ2

3


Flip-Flop: Timing Definitions

DATA

STABLE

DATA

STABLE

In

Out

t

t

t

φ

tsetup thold

tpFF


Delay vs. Setup/Hold Times

0

50

100

150

200

250

300

350

-200 -150 -100 -50 0 50 100 150 200

Data-Clk [ps]

Clk

-Ou

tpu

t [p

s]

Setup Hold

Minimum Data-Output

4


Pulse-Triggered Latches

Master-SlaveLatches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-TriggeredLatch

L1 L2 L

Flip-flops:


Propagation Delay Based Edge-Triggered

φ

In XN2

N1

Out

φ

In

X

Out

tpLH

= Mono-Stable Multi-Vibrator

5



Vdd

D

Clk

Q

Q

Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :



Clk

D

Q

Q

S

R

7474, SR latch as a second stage

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l First stage is a senseamplifier, precharged tohigh, when Clk = 0

l After rising edge of theclock sense amplifiergenerates the pulse onS or R

l The pulse is captured inS-R latch

l Cross-coupled NANDhas different propagationdelays of rising andfalling edges

Sense-amplifier-based flip-flop, DEC Alpha 21264, StrongARM 110


Maximum Clock Frequency

FF

’s

LOGIC

tp,comb

φ

Also:tcdreg + tcdlogic > thold

tcd: contamination delay =minimum delay

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Master-Slave Flip-Flop

φ

φ

φ

φ D

InA

B

φ

φ

Overlapping Clocks Can Cause

• Race Conditions

• Undefined Signals


Flip-flop insensitive to clock overlap

DIn

φ

φ φ

φ

VDDVDD

M1

M3

M4

M2 M6

M8

M7

M5

φ−section φ−section

CL1 CL2

X

C2MOS LATCH

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C2MOS avoids Race Conditions

DIn

1

M1

M3

M2 M6

M7

M5

1

DIn

VDDVDD

M1

M4

M2 M6

M8

M5

0 0

VDDVDD

(a) (1-1) overlap (b) (0-0) overlap

X X


Pipelining

RE

G

φ

RE

G

φ

RE

G

φ

log.

RE

G

φ

RE

G

φ

RE

G

φ

.

RE

G

φ

RE

G

φ

logOut Out

a

b

a

b

Non-pipelined version Pipelined version

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Pipelined Logic using C2MOS

InF Out

φ

φ

VDD

φ

φ

VDD

φ

φ

VDD

C2C1

GC3

NORA CMOS

What are the constraints on F and G?


Example

1

φ

φ

VDD

φ

φ

VDDVDD

Number of a static inversions should be even

10


NORA CMOS Modules

φ

φ

VDDVDD

PDN

φ

In1In2In3

φ

VDD

PUN

φ

φ

Out

φ

φ

VDD

Out

VDD

PDN

φ

In1In2In3

φ

VDD

In4

In4

VDD

(a) φ-module

(b) φ-module

Combinational logic Latch


TSPC - True Single Phase Clock Logic

M1

M2

M3

VDD

In

Out

φ

φ

M1

M2

M3

VDD

In

Out

φ

φ M1

M2

M3

VDD

In

Out

φ

M1

M2

M3

VDD

InOut

φ

Precharged N Precharged P Non-precharged N Non-precharged P

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φ

VDD

Outφ

VDD

φ

VDD

φ

VDD

InStatic

Logic

PUN

PDN

Including logic into

the latch

Inserting logic between

latches


Doubled TSPC Latches

φ

VDD

Out

φ

VDD

Doubled n-TSPC latch

Inφ

VDD

Outφ

VDD

Doubled p-TSPC latch

In

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φ

VDD

Outφ

VDD

φ

VDD

φ

VDD

InStatic

Logic

PUN

PDN

Including logic into

the latch

Inserting logic between

latches


Master-Slave TSPC Flip-flops

φ

VDD

D

VDD

φ

VDD

D

φ

VDD

φ

VDD

D

VDD

φ

φ

Dφ

VDD

φ

VDD

D

VDD

φ

φD

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY

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Latches versus Registers

CLK

QD

CLK

QD

clk

In

Out

G

In Out In Out

Positive Latch Negative Latch

G

clk

In

Out

Outstable

Outfollows In

Outstable

Outfollows In

Latch: level-sensitive circuit passing the input to the outputwhen the latch is enabled - otherwise it is in hold

Edge-triggered register: samples the input on clock transition


Edge Triggered Flip-Flop

φ

S

R

Q

Q

Q

J

K

Q

QJ

KQ

>φ

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JK Latch

S

R

Q

Q Q

J

K

φ

QJ

K Q

Jn Kn Qn+1

0

0

11

0

1

01

Qn0

1Qn

(b)

(c)

Q

(a)φ


Other Flip-Flops

QJ

K Q

φ

T

φQJ

K Q

φφ

D

Q

Qφ

T Q

Qφ

D

Toggle Flip-Flop Delay Flip-Flop

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Multivibrator Circuits


Schmitt Trigger

In Out

Vin

Vou tV O H

V O L

VM – VM +

•VTC with hysteresis

•Restores signal slopes

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Noise Suppression usingSchmitt Trigger

VM+

VM–

VoutVin

t tt0 t0 + tp


CMOS Schmitt TriggerVDD

Vin Vout

M1

M2

M3

M4

X

Moves switching thresholdof first inverter

17


Schmitt TriggerSimulated VTC

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

0.0

1.0

2.0

3.0

4.0

5.0

VX (V

)

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

0.0

2.0

4.0

6.0

Vou

t (V

)

VM-

VM+


CMOS Schmitt Trigger (2)

In

VDD

VDD

Out

M1

M2

M3

M4

M5

M6

X

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Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T


Transition-Triggered Monostable

DELAY

td

In

Outtd

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Monostable Trigger (RC-based)

VDD

InOutA B

C

R

In

B

Outt

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.


Astable Multivibrators (Oscillators)

0 1 2 N-1

0 1 2 3 4 5

t (nsec)

-1.0

1.0

3.0

5.0

V (

Vol

t)

V1 V3 V5

Ring Oscillator

simulated response of 5-stage oscillator

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Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

t pH

L (

nsec

)

propagation delay as a functionof control voltage


Relaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC

Sequential Logic (2) Multivibrator Circuits

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