Obtaining J-K%2C D%2C and T Excitation Equations

8/22/2019 Obtaining J-K%2C D%2C and T Excitation Equations

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IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 4, NOVEMBER 1996 519

Obtaining J-K, D, and T Excitation EquationsDirectly from State Transition DiagramsRicha rd S. Sand ige , Senior Member, IEEE

Abstract- This paper presents techniques for obtaining J -IC, D , and T excitation equations for synchronous state machinedesigns directly from state transition diagrams. Classical designsusing li-maps (Karnaugh maps) are time consuming to draw anddifficult to use when large designs are involved. Computer toolsare very valuable for assignmentsoutside of the classroom, that is,for homework assignments, laboratory assignments, and specialprojects, but computers are not generally provided for studentuse on quizzes and exams. The techniques for obtaining flip-flopexcitation equations presented in this paper apply to large orsmall designs. The excitation equations that are obtained usuallyneed to be reduced prior to implementation. Although equationreduction is not the theme of this paper, some of the excitationequations will be obtained using algebraic reduction, li -mapreduction, and computer tool reduction to allow comparisons tobe made.

I. INTRODUCTIONNE MAJOR disadvantage of using either classical design0 ia K-maps [l], [2] or a computer tool [ 3 ] to obtainexcitation equations is the fact that the procedures are ratherrote and therefore students are not forced to completelyunderstand the requirements of a specific flip-flop in a de -sign. The techniques presented in this paper allow studentsto evaluate synchronous state machine designs via a state

transition diagram or an equivalent algorithmic state machine(ASM) chart [4]o determine the specific requirements for theexcitation inputs of the flip-flops being using in the designs.If reduced excitation equations are to be obtained by hand,the resulting excitation equations can either be minimizedalgebraically or via K-ma ps. A computer tool can also be usedto minimize the resulting excitation equations for assignmentsoutside of class. In the first digital design course taught by theauthor at the University of Wyoming [5] ,student acceptanceof the techniques described in this paper has been extremelygood.Designs for this paper center around the sample synchron ouscircuit [6]presented in Section 11.The techniques for obtainingthe excitation equations for J - K flip-flops is presented inSection 111. Techniques for obtaining the excitation equationsfo r D and T flip-flops are presented in Sections IV and Vrespectively. The designs are checked using solutions obtainedby K-maps and solutions obtained by the computer toolPLDesigner-XL.

Manusc ript received July 7, 1993; revised May 24 , 1995.The author is with the Department of Electrical Engineering, University ofPublisher Item Identifier S 0018-9359(96)08738-9.Wyoming, Laramie, W Y 82071 USA.

Fig. 1. State transition diagram of the sample synchronous circuit.

11. TH E SAMPLE YNCHRONOUSIRCUITThe sample synchronous circuit used in this paper has twoinput variables XI and X2 , two output variable 21 and 22 ,and three states in its main sequence as illustrated by the

state transition diagram shown in Fig. 1. State d, i.e., theunused, illegal, or dead state, is used to illustrate how to handledont cares. The state assignment was picked to minimizethe output equations for 21 and 2 2 such tha t 21 = y land 2 2 = y2, where the State = y1y2 uses a minimumnumber of flip-flops encoding scheme (less than one flip-flop per used state-actually [log, s] flip-flops for s usedstates or rlog,3] = 2 flip-flops for three used states, where[log, 31 = [ln 3/ In 21 = 2, i.e., the smallest integer greaterthan or equal to log, 3).

111. OBTAINING THE EXCITATIONEQUATIONSOR J-K FLIP-FLOPS

Consider the characteristic table for the J -K flip-flop [51,[7], Table I. Lower case y is used as the present state variablewhile upper case Y is use as the next state variable. TheBoolean function for Y , he characteristic equation of the J -K flip-flop, is written directly from the characteristic table asfollows:

0018-9359/96$05.00 0 1996 IEEE

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520

TABLE I

IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO 4, NOVEMBER 1996

TABLE I1

y1 1 0

Yi @ a ~i +yi .E,or i =1 . .(n=number of flip-flops).

1 to 0 han e of i, clear conditionwhere - = dont care- -K i = Y i w h e n y i = l ( y i = O ) , f o r i = l . . . n

(n= number of flip-flops). ( 5 )Equations (4) and ( 5 ) are expressed in truth table format,called the J-K excitation table, as shown in Table 11. Thistable is used when deriving excitation equations for J-Kflip-flops via the classical K-Map design approach.The technique for writing the J - K excitation equationsdirectly from state transition diagrams is presented as follows:

i2)Using (2) the excitation inputs Ji and Ki are obtained as

roilow s:Yz @Yz= (y2. J?,+yz.E)Yz0 = ($ . J i +yz .E ) Y i0 @3(G.i +y i .E)(@. Ji +y i . K i )(3.i +y i . K i )=0 @ Y i($. J i +yz . E ) Y i

@ Y i @ (y.. i +yi .E)(3)

(4)Jz. =Yz when $= l ( y i =0) , for z =1 . .n

( n= number of flip-flops)

Equation Comment. (0 to 1 condition)+C(u nus ed state) .-

J i =C(p resen t s tate) 0 to 1 changes of y iunused statewhen $= l ( y i =0) ( 6 )Ki=C(p resen t s tate)e (1 to 0 condition)+C(unused sta te) - - 1 o 0 changes of yzunused statewhen yz =1(G 0 ) . (7)

Observe that J i is generated from set conditions (zero toone changes of y i ) while Ki s generated from clear conditions(one to zero changes of y i ) . This technique may be referred to

_ _J1= y l .y2. X1 0 to 1 change of y l , set condition+ e y2 X1 . 0 to 1 change of y l , set condition+y l y2 -when 3 =l ( y 1 =0)

unused state, dont careJ1 =$ . X l + y 2 . X I . x2

_ - -K1 =y l .y2. X1 .X 2 1 o 0 change of y l , clear condition1 to 0 change of y l , clear conditionunused state, dont care

+y l .$. E. 2+y l .y2. -w h e n y l = l ( s = O ) K l =y 2 - X l . X2 +y 2 - X l . X2 +y 2 -- - - -_ _ -5 2 =y 1 . y 2 . x1 . x 2 0 to 1 change of y2, set condition+y l .$. m. 2 0 t o 1 change of y2, set condition+y 1 . y2 - unused state, dont care

when $= l ( y 2 =0 ) J 2 =y l .X 1 X 2 + y l . X 1 X 2- ---2 =9y 2 X1 .X 2 1 to 0 change of y2, clear condition1 to 0 change of y 2 , clear conditionunused state, dont careK 2 =y 1 . X 1 X 2 +g . 1 . m + 1 . -.

+g . 2 .X1 .+y 1 . y 2 . -when y2 = l( $ =0) _ - -

(9)



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SANDIGE: OBTAINING J-K, D, AND T EXCITATION EQUATIONS DIRE(

yly2blX2J1

3TLY FROM STATE TRANSITION DIAGRAMS

yly2\XlX2K1 =

J1 = S * X 1 + X 1 -(a )

yly2\XlX252 =

YlYK2 =

,2\XlX2

52 1

-52 = X1*X2(c ) (d)Fig. 2.reduced equation. (d) I i 2 map with reduced equation.J - I C excitation equation reduction using IC-maps. (a) J 1 map with reduced equation. (h) Ii l map with reduced equation. (c) J 2 ma p with

as the setklear method for writing J-K excitation equations.The excitation equations (8)-(11), shown at the bottom ofthe previous page, are written by inspection from the statetransition diagram of the sample synchronous circuit using (6)and (7), respectively.For the small sample synchronous circuit design in thispaper, like those on quizzes and exams, excitation equationreduction for J - K flip-flops is not difficult and can be obtainedalgebraically as illustrated belowJ l = $ . X l + y 2 . X l . X 2

=x1. $ + y 2 .E)= X l . ( $ + x 2 )=2.1 +x1 . x2=8 . I. (xa+X2) +y 2 . -=y 2 . x l+ 2 . -=xi +2. -

K 1 = $ . X T * x a + $ . X T . X 2 +y2. -- --x 152=9. i . 2 +y 1 .xi . 2

=37. 2. (S+l )-X l . X 2K 2 =iji. I.x2+3 . 1.x2+y 1 . -=3 . 2. XI SXI) +y l .-

=y l . X 2 + y l . -=x 2 + y l . --_ _ _=x2.Excitation equation reduction is simple combinational logicreduction that can also be performed using K-maps as shownin Fig. 2(a)-(d) for (8)-(11). Fig. 3(a) shows the flow map forthe sample synchronous circuit in K-map format with the stateassignment filled in. Fig. 3(b)-(e) is drawn and plotted usingthe excitation table for the J-K flip-flop. Observe that the

reduced, i.e., minimum sum of products equations in this case,obtained using the setklear method after algebraic reductionandor K-map reduction agree with those obtained using theclassical K-map design approach as expected.The PLDesigner-XL computer tool reduces large or smallequations. The design source file to reduce (8)-( 11) is writtenas

INPUT y l , y2,X1, X 2 ;OUTPUT J1,K1,52,K2;J1=/ y 2 * x 1 + y2*Xl*/X2;K l =/y2*/Xl*/X2 + y2*/Xl*X2 +y2*.x.;5 2 =/yl*/Xl*X2 +yl*/Xl*X2;K2 =/yl*/Xl*/X2 + yl*Xl*/X2 +yl*.X.;

Compiling the design source file using the Quine-McCluskey equation reduction method results inREDUCED EQUATIONS:J1. EQ N =X1*/X2 +Xl*/y2; (2 terms, 3 symbols)K1. EQ N =/X1; (1 term, 1 symbol)5 2 . EQ N =/Xl*X2; (1 term, 2 symbols)K2. EQ N = /X2; (1 term, 1 symbol).To obtain a complete set of equations for the samplesynchronous circuit, i.e., those available for fuse map im-plementation in a programmable logic device (PLD), thefollowing design source file was written using the setklearequations (8)-(11). Notice in the new design source file thatthe inputs must be changed, the J-K flip-flop outputs must bespecified and clocked, and the left side of each equation mustbe modified, i.e., all variables had to be present in all dontcare product terms (product terms ending with .X.), to insure



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522 IEEE TRANSACTIONS

y 1y2\x 1 2 /z122ON EDUCATION, VOL. 39, NO. 4. NOVEMBER 1996

00 01 11 10J1

y 1y2\x 1x2J2

0001

l o

/--

K1

Y l YK2 =

cK2 = X2(4 ( e )

Fig. 3.equation. (d) J 2 map fo r classical solution with reduced equation. (e) K 2 map for classical solution with reduced equation.(a) Flow map for sample synchronous circuit. (b) J1 map for classical solution with reduced equation. (c) K1 map for classical solution with reduced

proper equation reduction TABLE I11INPUT X1,X 2 , CK;J K P L O P O U T PU T y l , y 2 C L O C K E D B Y C K ;y 1 . J =/y2*Xl+ y2*Xl*/X2;y1.K =/y2*/Xl*/X2 +/y2*/XI*X2 +y l*y2* .X. ;y2.J =/yl*/Xl*X2 +yl*/Xl*X2;y2.K =/yl*/Xl*/X2 +/yl*Xl*/X2 +yl*y2*.X.;The following design equations were obtained after com-piling the design. Note that y 1 . J represents the J inputto flip-flop one, y1.K represents the K input to flip-flopone, y2. represents %e J input to flip-flop two, and y2.krepresents the K input to flip-flop two.

REDUCED EQUATIONS:y1.J =Xl*/X2 +Xl*/y2;/(2 erms, 3 symbols)y1.K =/Xl;(1 erm, 1 symbol)y l . C L K =CK;/(l term, 1 symbol)y2 . J =/ X l * X 2 ; I ( 1 term, 2 symbols)y 2 . K = / X 2 ; ( 1 t er m, 1 symbol)y2.CLK =CK;/(l term, 1 symbol).

method after algebraic reduction and/or K-map reductionand with those obtained using the classical K-map designapproach. The signal yl. CL K represents the CLK input of flip-flop one, and y2.CLK represents the CLK input of flip-floptwo.Iv. OB TAI NI NG THE EXCITATION

EQUATIONS FOR D FLIP-FLOPSThe characteristic table for the D flip-flop [SI is listedin Table 111. The Boolean function for Y , he characteristicequation of the D flip-flop, is obtained by inspe ction as Y =Dor in general asY i =D z, fo r z =1 ...n (n= number of flip-flops). (16)The excitation input Di is obtained as follows:

Note that the reduced equations for y l . J , yl.K, y 2 . 4 a ndy2 .K agree with those obtained earlier using the setlclear

Y i @ Yi=Di @ Yi0 =D i @ Yi



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SANDIGE: OBTAINING J-K, D, AN D T EXCITATION EQUATIONS DIRECTLY FROM STATE TRANSITION DIAGRAMS

0 1 10 0 1- - -0 1 1

52 3

0 00 11 01 1

g l y 2 1 x i

11 -D1=i!0 00101

0 to 1 change of y i , set condition1 to 1 change of yi , hold 1 condition

c

'D l = 2 ~ x 1 X l - z D2 = y 2 . n + z * X ZFig. 4. D excitation equation reduction using A-maps. (a) DI map with reduced equation. (b) 0 2 map with reduced equation.

0 Di =Di@ Yi@ Di TABLE IVDi=Yi, o r i =l . . . n

(n = number of flip-flops). (17)Expressing (17) in truth table format results in the Dexcitation table, Table IV. This table is usually bypassedwhen obtaining excitation equations for D flip-flops using theclassical K-Map design approach by simply solving for Yiand substituting Yi or Di.The technique for writing the D excitation equations directlyfrom state transition diagrams is presented as

Equation CommentDi=C(p resen t s tate). 0 to 1 condition)+C(p resen t s tate). 1 to 1 condition)+C(u nuse d sta te) .- unused state. (18)

Observe that Di is generated from set conditions (zero toone changes of yi) or hold one conditions (one to one changesof yi). This technique may be referred to as the "set or hold1 method" for writing D excitation equations. The excitationequations (19) and (20), shown at the bottom of the page, arewritten by inspection from the state transition diagram of thesample synchronous circuit using (18).Since two conditions (set or hold 1) must be used to deriveeach D excitation equation, algebraic equation reduction isusually difficult. The preferred method to use for equation

0 to 1 changes of yi1 o 1 changes of yi

reduction for large or small designs is a computer tool ifone is available. For small designs like those on quizzes andexams, the preferred method of equation reduction is to enterthe combinational logic excitation equations into K-maps thenobtain the minimum equations as illustrated in Fig. 4(a) and(b), for (19) and (20), shown at the bottom of the page.

The design source file to reduce (19) and (20) using thecomputer tool PLDesigner-XL is listed as follows:

INPUT y l , $2, X1, X 2 ;OUTPUT D1,DZ;D1 = / y l * / y 2 * X 1 + / y l * y 2 * X I * / X Z+y l * / y 2 * X l + y l * y 2 * . X . ;

+ y l*yZ*X2 +yl*y2*.X.; .0 2 =/ y l * / y 2 * / X l * X 2 +y l * / y 2 * / X I * X ZCompiling the design source file using the Quine-

McCluskey equation reduction m ethod results in the following

_ _D1= ~ 1 .2 .1 0 to 1 change of y l , set condition0 to 1 change of y l , set condition1 to 1 change of y l , hold 1 conditionunused state, don't care

+$. y2 .X1 .+ y l . $ . X l+y l .y 2 . -

=iji. . xl+ ji.2. x1. '2+ y l 8 .l+ l .y 2 . -0 2 =g . . 1. 2+y l .$.+$. y 2 .x 2+y1 .y2 .-

0 to 1 change of y2, set condition0 to 1 change of y2, set condition1 o 1 change of y2, hold 1 conditionunused state, don't care

X 2

=iji $. xi . 2 +x 2 +y l .$. xi . 2 +g . 2 . x 2 +y l .y 2 . -.Authorized licensed use limited to: Air University. Downloaded on June 19, 2009 at 00:43 from IEEE Xplore. Restrictions apply.


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524

0 11 01 1

TABLE V

110

0 to 1 change of yz, set condition1 to 0 change of yz, clear condition*equations:

IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 4, NOVEMBER 1996

TABLE VI

0 0 10

Expressing (22) in truth table format results in the Texcitation table, Table VI. This table is used when derivingexcitation equations for T flip-flops via the classical K-Mapdesign approach.The technique for writing the T excitation equations directlyfrom state transition diagrams is presented as follows:

REDUCED EQUATIONS:D1.EQN =X l * / X 2 +X l * / y 2 ; ( 2 terms, 3 symbols)D2.EQN T X l * X 2 +X2*y2 ; ( 2 terms, 3 symbols).Observe that the reduced equations obtained using the setor hold 1 method after K-map reduction agree with thereduced equations obtained using the computer tool.

V. OBTAINING THE EXCITATIONQUATIONSOR T FLIP-FLOPSThe characteristic table for the T flip-flop [5] is listedin Table V. The Boolean function for Y , he characteristicequation of the T flip-flop, is obtained as follows:

Y = g . T + y . TY i=y i @ T i , fo r i =1 .. n

( n=number of flip-flops). (21)The excitation input Ti is obtained as follows:

Y i @ Y i =y i @T i@ Y i0, = i @Ti@ Yi

0 $ T i =y i $ T i $ Y i @ TiT i =y i @ Y i @ 0T i =y i @ Yi,or i = l . . . n

(n= number of flip-flops). (22)

Equation CommentTi=C(p resen t s ta te)

. (0 to 1 condition)+C(pr esen t s ta te). (1 o 0 condition)+C(u nuse d sta te) -0 to 1 changes of yi1 o 0 changes of y iunused state. (23)Observe that Tz is generated from set conditions (0 to 1changes of yz) or clear conditions (one to zero changes of y i ) .This technique may be referred to as the set or clear methodfor writing T excitation equations. The excitation equations(24) and (25), shown at the bottom of the page, are writtenby inspection from the state transition diagram of the samplesynchronous circuit using ( 23) .Like D excitation equations, T excitation equations arederived with two cond itions usually m aking algebraic equationreduction difficult. The preferred method to use for equationreduction for large or small designs is a computer tool.For small designs in the classroom, the preferred method toperform equation reduction is to enter the combinational logicexcitation equations into K-maps then obtain the minimumequations as illustrated in F ig. 5(a) and (b) for (24) and

(25).

- _T 1= y l . y 2 . X l 0 to 1 change of y l , set condition0 to 1 change of y l , set condition1 o 0 change of yl, clear condition1 o 0 change of y l , clear conditionunused state, dont care

+5 y 2 .X1 .x2+y l . y 2 . X1 .X 2+y l .g. X 2+y l . y2 -

- - -= j i . y 2 . X l + i J . y2 .x1 x 2 + y l . $ . x l . ; ! + y 1 . $. xi .2 +y l . y 2 . -

T 2 = g . $ * X Z . X 2 0 to 1 change of y2, set condition0 to 1 change of y2, set condition1 to 0 change of y2, clear condition1 to 0 change of y 2 , clear condition

unused state (dont care)

+y1 .$. s X 2+9. 2 .X 1 .X 2+g . 2 .X1 .x2+y 1 . y 2 . -- _

=3.8.i . 2 +y l .$2. T i .x2+3 . 2 . XI.x2+5 . 2 . x1.x2+y l . y 2 . -.Authorized licensed use limited to: Air University. Downloaded on June 19, 2009 at 00:43 from IEEE Xplore. Restrictions apply.


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SAN1XGE: OBTAINING J-K, D, AND T EXCITATION EQUATIONS DIRLECTLY FROM STATE 525

Y YT1 =

, 2 t ( lX2

TRANSITION DIAGRAMS

TI = y 1 . x + g.Z.x1 + 3 . x 1 . 5 T2 = $.X1.X2 + y 2 . S(a) (b)

Fig. 5. T excitation equation reduction using K-maps. (a) T1 map with reduced equation. (b) T2 map with reduced equation.

The design source file to reduce (24) and (25) using thecomputer tool PLDesigner-XL is listed as follows:INPUT y l , y 2, X1, X2;OUTPUT TI , T2;T1 =/yl*/y2*X1+ /yl*y2*Xl*/X2

+yl*/y2*/Xl*/X2 +yl*/y2*/Xl*X2+yl*y2*.X.;+ yl*y2*/Xl*/X2 + yl*y2*Xl*/X2+yl*y2*.X.;.

T2 =/yl*/y2*/Xl*X2 +yl+/y2*/Xl*X2Compiling the design source file using the Quine-McCluskey equation reduction method results in the followingequations:

REDUCED EQUATIONS:T1.EQN =Xl* /X2* /yl+ Xl*/yl*/y2+/Xl*yl;(3 erms, 4 symbols)

(2 terms, 3 symbols).Observe that the reduced equations obtained using the setor clear method after K- ma p reduction agree with the reducedequations obtained using the computer tool.

T2.EQN =/Xl*X2*/y2 +/X2*y2;

VI. CONCLUSIONThis paper has presented techniques for obtaining J - K , D ,an d T excitation equations for synchronous circuits directlyfrom state transition diagrams. The three methods presentedwere the sevclear meth od for J-K flip-flops, the set o r hold

1 method for D flip-flops, and the set or clear method forT flip-flops. Students tend to gain a superior understandingof each type of flip-flop and the role it plays in the designof synchronous circuits by using these methods. The J-Kflip-flop excitation equations were shown to be the easiestto obtain. Since the derivation of J-K flip-flop excitationequations only require one condition (set for Jlclear for K) ,algebraic equations reduction is not difficult for small designs.The sample synchronous circuit used in this paper has anunused state to illustrate how to handle don t cares. The unused

state was also used as a dont care to simplify the excitationequations. Since modern designs generally use power-up resetto initialize synchronous circuits to a used state at turn onor when a power line glitch occurs, unused states can beused in this manner. The derivation of D an d T excitationequations each require two conditions (set or hold 1 fo r Dand set or clear for T ) making algebraic equation reductiondifficult. Several methods were presented for obtaining re-duced excitation equations. For small designs on qu izzes andexams, K-map reduction was stressed as a good techniquefor excitation equation reduction. The preferred method forexcitation equation reduction is to use a computer tool suchas the one used in this paper, PLDesigner-XL. With such atool a final design can also be implemented in a PLD frommajor vendor.

REFERENCESV. T. Rhyne, Jr., Fundamentals of Digital Systems Design. EnglewoodCliffs, NJ : Prentice-Hall, 1973.R. S . Sandige, The transition-map-entered-variable (T-MEV) mappingtechnique for sequential machine design, Doctoral dissertation, TexasA&M Univ., 1978.PLDesigner-XLTM users guide, The next generation in programmablelogic design synthesis, Version 3.2, MINC Incorporated, ColoradoSprings, CO, i994.C. R. Clare, Designing Lonic Systems Using State Machines. Ne w.York McGraw-Hill, 1973.R. S. Sandiae. Moder n Digital Design. New York: McGraw-Hill, 1990.S . H. Ungir , The Essen& o Losic Circuits. Englewood Cliffs, NJ:Prentice-Hall, 1989.C. H. Roth Jr., Fundamentals ofLogi c Design, 4th ed. St. Paul, M NWest, 1992.R. S. Sandige 73.3 bistable devices, in The Electrical Engineer-ing Handbook, R. C. Dorf, Ed. Boca Ratan, FL: CRC, 1993, pp.1635-1641.

Richard S. Sandige (S63-M64-SM 90) received the B.S.E.E. and M.S.E.E.degrees from West Virginia University, Morgantow n, WV, in 1963 and 1969,respectively, and the Ph.D. degree in electrical engineering from Texas A&MUniversity, College Station, TX, in 1978.He is currently a Professor in the Department of Electrical Engineering,University of Wyoming, Laramie. Prior to joining the staff at the Universityof Wyoming, he worked for ten years as a Member of the Technical Staff inthe Research and Development Laboratory at Hewlett Packard, Fort Collins,CO. His research interests include PLDs and FPGAs and their applications indigital design and m icroprocessor systems. He currently supports the researchand development activities of Minc Incorporated, a technology leader inprogrammable logic synthesis tools.

Obtaining J-K%2C D%2C and T Excitation Equations

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