Nonlinear & Neural Networks LAB.

CHAPTER 7

MULTI-LEVEL GATE CIRCUITS / NAND AND NOR GATES

7.1 Multi-Level Gate Circuits7.2 NAND and NOR Gates7.3 Design of Two-Level Circuits Using NAND and NOR Gates7.4 Design of Multi-Level NAND- and NOR-Gate Circuits7.5 Circuit Conversion Using Alternative Gate Symbols7.6 Design of Two-Level, Multiple-Output Circuits7.7 Multiple-Output NAND and NOR Circuits

Nonlinear & Neural Networks LAB.

Objectives

Topics introduced in this chapter:

• Design a minimal two-level or multi-level circuit

• Design or analyze a two-level gate circuit

• Design or analyze a multi-level gate circuit

• Convert circuits by adding or deleting inversion bubbles

• Design a minimal two-level or multiple-output circuit using

Karnaugh maps

Nonlinear & Neural Networks LAB.

7.1 Multi-Level Gate Circuits

Four-Level Realization of Z

• Terminology

AND-OR, OR-AND, OR-AND-OR, AND and OR

Nonlinear & Neural Networks LAB.

7.1 Multi-Level Gate Circuits

Three-Level Realization of Z

HCFGABFGEDCEDAB

HFGEDCABZ

Nonlinear & Neural Networks LAB.

7.1 Multi-Level Gate Circuits

Example : Multi-Level Design Using AND and OR Gates

14,13,10,6,5,1,,, mdcbaf

Two-level AND-OR gate

Nonlinear & Neural Networks LAB.

7.1 Multi-Level Gate Circuits

badcbadc

dacdbcdcbdcaf

cbacdcbadcf

cbadccbadcf

Three-level OR-AND-OR gateFrom 0’s on the Karnaugh map

f

Two-level OR-AND gate

Nonlinear & Neural Networks LAB.

7.1 Multi-Level Gate Circuits

badcbadcf

Using YZXZXYX

If we multiply out bad and bad

dbdacbddacf

Three-level AND-OR-AND gate

bdadcbdadc

badcbadcf

Nonlinear & Neural Networks LAB.

7.2 NAND and NOR Gates

NAND gate

CBAABCF

nn XXXXXXF 2121

Nonlinear & Neural Networks LAB.

7.2 NAND and NOR Gates

NOR gate

CBACBAF

nn XXXXXXF 2121

OR realized by using AND and NOT

Nonlinear & Neural Networks LAB.

7.2 NAND and NOR Gates

NAND gate realization of NOT, AND, and OR

AND realized by using OR and NOT

YXXY

Nonlinear & Neural Networks LAB.

7.3 Design of Two-Level Circuits Using NAND and NOR Gates

DeMorgan’s laws

Conversion of a sum-of-products to several other two-level forms

nn XXXXXX 2121

nn XXXXXX 2121

DCBCBA

DCBCBA

CDBCBA

CDBCBACDBCBAF

AND-OR

NAND-NAND

OR-NAND

NOR-OR

Nonlinear & Neural Networks LAB.

7.3 Design of Two-Level Circuits Using NAND and NOR Gates

DCBCBAF NOR-NOR-INVERT

DCABCACBA

DCABCACBA

DCACBACBA

DCACBACBA

DCACBACBAF

OR-AND

NOR-NOR

AND-NOR

NAND-AND

Nonlinear & Neural Networks LAB.

7.3 Design of Two-Level Circuits Using NAND and NOR Gates

Eight Basic Forms for Two-Level Circuits

Nonlinear & Neural Networks LAB.

7.3 Design of Two-Level Circuits Using NAND and NOR Gates

NAND-NOR

AND-OR to NAND-NAND Transformation

21212121 PPllPPllF

21, ll : literals 21,PP : product terms

Nonlinear & Neural Networks LAB.

7.4 Design of Multi-Level NAND- and NOR-Gates Circuits

•Procedure : multi-level NAND-gate circuits

- Simplify the switching function

- Design a multi-level circuit of AND and OR gates

- Number the levels starting with the output gate as level 1

- Replace all gates with NAND gates, leaving all interconnections

between gates unchanged

- Leave the inputs to levels 2,4,6,… unchanged

Nonlinear & Neural Networks LAB.

7.4 Design of Multi-Level NAND- and NOR-Gates Circuits

Example : Multi-Level Circuit Conversion to NAND Gates

kjihgfedcbaF 1

Nonlinear & Neural Networks LAB.

7.5 Circuit Conversion Using Alternative Gate Symbols

Inverter

Alternative Gate Symbols

Nonlinear & Neural Networks LAB.

7.5 Circuit Conversion Using Alternative Gate Symbols

NAND Gate Circuit Conversion

Nonlinear & Neural Networks LAB.

7.5 Circuit Conversion Using Alternative Gate Symbols

Conversion to NOR Gates

Nonlinear & Neural Networks LAB.

7.5 Circuit Conversion Using Alternative Gate Symbols

Conversion of AND-OR Circuits to NAND Gates

Nonlinear & Neural Networks LAB.

7.6 Design of Two-Level,Multiple-Output Circuits

Example : Design a circuit with four inputs and three outputs

15,14,13,12,7,3,,,

15,13,12,11,7,3,,,

15,14,13,12,11,,,

3

2

1

mDCBAF

mDCBAF

mDCBAF

Karnaugh Maps for Equations

Nonlinear & Neural Networks LAB.

7.6 Design of Two-Level,Multiple-Output Circuits

Realization of Equations Multiple-Output Realization of Equations

Nonlinear & Neural Networks LAB.

7.6 Design of Two-Level,Multiple-Output Circuits

Example : Design a multiple-output circuit with 4-inputs and 3-outputs

15,14,13,9,8,7,6

15,14,11,10,7,6,5,3,2

15,13,11,10,9,8,7,5,3,2

3

2

1

mf

mf

mf

Karnaugh Maps for Equations

Nonlinear & Neural Networks LAB.

7.6 Design of Two-Level,Multiple-Output Circuits

Minimized equations

dca

or

abd

cbabcf

bdacf

bacbbdf

3

2

1

10gates,

25gate input

The minimal solution

abdcbabcf

bdacf

cbcbaabdbdaf

3

2

1

8 gates22 gate inputs

Nonlinear & Neural Networks LAB.

7.6 Design of Two-Level,Multiple-Output Circuits

Determination of Essential Prime Implicants for Multiple-Output Realization

Nonlinear & Neural Networks LAB.

7.7 Multiple-Output NAND and NOR Circuits

Multi-level Circuits Conversion to NOR Gates

fedcbaF 1 hfegcbaF 2