Karnaugh-map usage
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Logic System Design I 4-36 Karnaugh-map usage Plot 1s corresponding to minterms of function. Circle largest possible rectangular sets of 1s. – # of 1s in set must be power of 2 – OK to cross edges Read off product terms, one per circled set. – Variable is 1 ==> include variable – Variable is 0 ==> include complement of variable – Variable is both 0 and 1 ==> variable not included Circled sets and corresponding product terms are called “prime implicants” Minimum number of gates and gate inputs
Transcript of Karnaugh-map usage
Logic System Design I 4-36
Karnaugh-map usage
Plot 1s corresponding to minterms of function.Circle largest possible rectangular sets of 1s.
– # of 1s in set must be power of 2– OK to cross edges
Read off product terms, one per circled set.– Variable is 1 ==> include variable– Variable is 0 ==> include complement of variable– Variable is both 0 and 1 ==> variable not included
Circled sets and corresponding product terms are called “prime implicants”
Minimum number of gates and gate inputs
Logic System Design I 4-37
Prime-number detector
Logic System Design I 4-38
Resulting Circuit.
Logic System Design I 4-39
Another example
Logic System Design I 4-40
Yet another example
Distinguished 1 cellsEssential prime implicants
Logic System Design I 4-41
Another Example
F(W,X,Y,Z) = Σm(0,1,2,4,5,6,8,9,12,13,14)
Logic System Design I 4-42
Another Example
F(W,X,Y,Z) = Σm(0,1,2,3,6,8,9,10,11,14)
Logic System Design I 4-43
Another Example
F(W,X,Y,Z) = Σm( )
Logic System Design I 4-44
Don’t Cares
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00 01 11 10N3 N2
N1 N0
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1 1 d
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N3
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(a)00 01 11 10
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1 1 d
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F = N3′ • N0 + N2′ • N1
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N3′ • N0
N2′ • N1
N2 • N0
F = ΣN3,N2,N1,N0(1,2,3,5,7) + d(10,11,12,13,14,15)
Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e
Logic System Design I 4-45
Another Example
F(W,X,Y,Z) = Σm(0,1,2,3,6,8,9,10,11,14) + d(7,15)
Logic System Design I 4-46
Another Example
F(W,X,Y,Z) = Σm( ) + d( )
Logic System Design I 4-47
Resulting Circuit
F(W,X,Y,Z) = Σm( ) + d( )
Logic System Design I 4-48
Another Example
F(V,W,X,Y,Z) = Σm(0,1,2,3,16,17,18,19,20,21,22) + d(23,30,31)
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V=0 V=1
Logic System Design I 4-49
Resulting Circuit
F(V,W,X,Y,Z) = Σm(0,1,2,3,16,17,18,19,20,21,22) + d(23,30,31)
Logic System Design I 4-50
Another Example
F(V,W,X,Y,Z) = Σm( ) + d( )
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Logic System Design I 4-51
Current Logic Design
Lots more than 6 inputs -- can’t use Karnaugh mapsUse software to synthesize logic expressions and
minimize logicHardware Description Languages -- VHDL and Verilog
