International Journal of VLSI Design and Technology (Vol 2 Issue 2)

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International Journal of

VLSI Design and Technology

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Basic MOS models, spice models

Frequency response stability and noise issues in amplifiers

CMOS analog blocks: current sources and voltage references

Differential amplifier op-amp and ota design

Frequency synthesizers and phased lock-loop

Non-linear analog blocks: comparators, charged-pump circuits and multipliers

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Analog interconnects and analog testing and layout

12 low voltage and low power analog

Electronic design automation

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From the Editor's Desk

Dear Readers,

We would like to present, with great pleasure, the inaugural volume of a new scholarly

journal, International Journal of VLSI Design and Technology. This journal is part of the

VLSI Design and Technology, and is devoted to the scope of present Electronics issues,

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papers at excellently, well-time & successfully.

International Journal of VLSI Design and Technology focuses on original high-quality research in the realm

of CMOS technologies, Basic MOS Models, SPICE Models, Frequency response, stability and Noise issues

in amplifiers, CMOS analog blocks: Current Sources and Voltage references, Differential amplifier, OPAMP

and OTA design, Frequency Synthesizers and Phased lock-loop, Non-linear analog blocks: Comparators,

Charged-pump circuits and Multipliers, Data converters, Analog Interconnects and Analog Testing and

Layout, 12 Low voltage and Low power Analog, Electronic design automation.

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and Telecommunication Engineering and solutions in the area.

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who supported us at every stage of the project. It is our hope that this fine collection of articles will be a

valuable resource for Electronics and Telecommunication Engineering readers and will stimulate further

research into the vibrant area of Electronics and Telecommunication Engineering.

Puneet Mehrotra

Managing Director

1. Energy Efficient Low-Voltage Dynamic Comparator S.K. Jain, C. Periasamy 1

2. Design and Analysis of 8T Full Adder Using 77 nm Technology M. Agnihotri, D. Bichwe 7

3. Temperature Dependent Performance Analysis of SWCNT Bundles as VLSI InterconnectsShilpa Agrawal, Ankit Kumar, Mayank Kumar Rai, Abhishek Shrivastava 11

4. Multilevel CMOS LDO-Voltage Circuit With Bi-CMOS LDO With and Without AmplifierKamlesh Sharma, Gajendra Sujediya, Abdul Naim Khan 18

5. Comparative Study of a 32 Bit Vedic Multiplier With a Conventional Binary MultiplierRohan Muley, Amrita Tuteja 26

Contents

IJVDT (2016) 1-6 © JournalsPub 2016. All Rights Reserved Page 1

International Journal of VLSI Design & Technology Vol. 2: Issue 2

www.journalspub.com

Energy Efficient Low-Voltage Dynamic Comparator

S.K. Jain*, C. Periasamy

Malviya National Institute of Technology, Jaipur, India

ABSTRACT

The blueprint of a comparator that is doubly tailed and with minimal voltage post amplifier

and stage of latching are explained deeply in this document. The main concern of the design

is in the comparator of traditional modes those are doubly tailed. The circuitry which is

traditionally doubly tailed is manipulated as per the need of minimal power and enhanced

operation in voltages with very minutes supply. In the technique of CMOS of 45 nm the

outcomes of simulation ensures the outcomes of assessments. It is also presented that by

minimizing the extent of channel, the absorption of power will also be deduced. The voltage

of 1.2 V that is furnished is absorbed as 4.11 μW in the comparator suggested here while it is

39.05 and 136.55 μW in the comparators those are currently in use.

Keywords: conventional dynamic comparator, double tail comparator, proposed dynamic

comparator, low power, fast operation

INTRODUCTION

Comparators are constituted as the main

formulation cells of an ADC. The ADCs

which possess a greater speed like the

flash tends for greater frequency, minimal

power along the area of chip. The

comparators that have a greater speed that

are deployed in methodology of UDSM-

CMOS face paucity of voltage when the

voltage thresholds are taken into account

in the appliances which had not been

deployed at a same level of furnished

voltage in the latest CMOS. So in the issue

of shortage in voltage, to form a

comparator that possesses a greater speed

is much more exigent. In order to

recompense the deducing voltage to attain

more speed some bigger transistors are

deployed which eventually demand for

greater section of die & power. The

outcomes obtained should be in the same

mode of input even a minimal voltage is

supplied in the structures of ADC that has

greater speed. There are several

methodologies like the boosting, the

transistors are driven by body, design of

mode of current and by making use of

process of double oxide which can manage

the supply of greater voltages which is

been deployed to attain the issues of

minimal voltages. The bootstrapping and

boosting are two methodologies which are

constituted in furnishing the supply,

voltage of clock and reference which will

be defined for a range of input and issues

of switching. These methodologies that put

a real impact, but they face some problems

in their accuracy in CMOS-USDM

terminologies. The methodologies that are

adopted by Blalock, they eliminate the

voltage of threshold like MOSFET driven

of body as an appliance that is of type of

exhaustion. A subsidiary modulator is

suggested on the terminologies which 1 bit

quantized.[1–3]

Apart from its superiorities

the transistors which are driven by body

bear some minute conductance in trans in

contrast to the {counterparts} in the

procedural {fabrication} like in all the

transistors which are constituted on the


International Journal of VLSI Design and Technology Vol. 2: Issue 2

www.journalspub.com

Design and Analysis of 8T Full Adder Using 77 nm Technology

M. Agnihotri1*, D. Bichwe

2

1Department of Electronics and Communication Engineering, Prashanti College of Engineering and

Technology, Ujjain, MP, India 2Department of Electronics and Communication Engineering, Guru Nanak Institute of Engineering and

Technology, Nagpur, India

ABSTRACT

The 8T full adder design has been proposed in this paper. The proposed design is based on

77nm technology. The power consumption by this design is reduced due to less number of

transistor count and efficient area is also get reduced by this proposed design. The design is

simulated with the help of Tanner tool. The simulation results are compared with the

conventional full adder design in terms of power consumption, area, time delay and power

delay product parameters.

Keywords: carry, full adder, 77nm technology, sum, transistor count

INTRODUCTION

Research efforts in the field of low power

VLSI (very large-scale integration)

systems have been increased due to

exponential growth of portable electronic

devices like laptops; audio/video based

multimedia and cellular communication

devices.[1]

With the increase in number of

transistors on chip, power consumption of

the VLSI systems is also increasing which

further increase to run time failures and

reliability problems. The packaging and

the cooling mechanism becomes more

costly with excessive power consumption.

Low power consumption is one of major

design criteria for IC designers at all levels

of design along with the delay and area

considerations. Proper functionality of

electronic device at low supply voltage is

also important consideration. In this paper,

we proposes a full adder design using less

number of transistor is to reduce power

consumption, less area, less power delay

and less power delay product.

PREVIOUS WORK

The full adder is basically 1 bit adder used

to perform arithmetic addition. It contains

three input bits like A, B, Cin and two

output bits Sum and Carry. The Boolean

expression for the Sum and Carry

functions is as shown below.

Sum = (AB)Cin

Cout = A.B + Cin (AB)

The conventional full adder circuit

contains much number of transistors. The

PMOS transistor acts as Pull up and

NMOS transistor acts as Pull down

transistor. It is very robust design but due

to more power consumption and more

number of transistor count, it not mainly

used in digital design. Figure 1 shows the

conventional transistor.

There are many proposed design for full

adder circuit. In recent years the different

types of full adder using various logic

styles have been proposed. Standard

CMOS 28 transistor adder having pull up

IJVDT (2016) 11-17 © JournalsPub 2016. All Rights Reserved


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Temperature Dependent Performance Analysis of SWCNT

Bundles as VLSI Interconnects

Shilpa Agrawal*, Ankit Kumar, Mayank Kumar Rai, Abhishek Shrivastava Department of Electronics and Communication Engineering, Thapar University, Patiala, India

ABSTRACT

Impact of temperature on delay in single walled carbon nanotube (SWCNT) bundle

interconnects has been analyzed. Temperature-dependent circuit model for metallic SWCNT

bundle is developed. The obtained results are matched with currently used copper

interconnects at 22 nm technology node. It is seen that SWCNT bundle interconnects are of

lower delay than copper interconnect with rise in temperature from 300K to 450K.

Keywords: carbon nanotube, delay analysis, interconnects, single walled carbon nanotube

INTRODUCTION

Due to scaling in die size, performance of

the copper based interconnects for global

signaling get debased due to the decrease

in conductivity of copper. In deep

submicron level, grain boundary scattering

and electron migration dominates

effectively.[1]

Material research lies out

that carbon nanotube (CNT) is a potential

candidate. CNTs are graphene tubes,

having diameter in range of nanometer,

formed by folding up graphene sheets of

carbon atoms with a proper chirality.[2]

Interconnects configured of these medium

are executed in an identical size scale as

the copper wires. CNTs have significant

lower resistivity than copper because of

the property of CNT that it has high

electron mean free path than the copper.[3–

5] Moreover a CNT wire can accommodate

a current density of 1010 A/cm2 or higher

value without any destruction.[6]

On the basis of structure CNTs are divided

into two groups: single-wall carbon

nanotubes (SWCNTs) and multi-wall

carbon tubes (MWCNTs).SWCNTs are

made up of single thin wall of graphene

sheet while MWCNTs are made up of

several concentric shells. On the basis of

conductivity CNTs are divided into two

groups: semiconducting CNTS (sCNTS)

and metallic CNTs (mCNTs) depending on

their chirality. Semiconducting CNTs are

used to form transistors whereas metallic

CNTs are used as interconnects.

Single tube of SWCNT has large

resistance due to which more than one

SWCNT, called as SWCNT bundle, are

combined parallel. By using SWCNT

Bundles, overall resistance is reduced and

it entitle CNT interconnect to be more

appropriate for copper interconnects at

advanced VLSI technology nodes.

The main objective of this study is to

develop the impedance parameters of

SWCNT bundles based interconnect as a

function of temperature.

This paper analyses the effect of

temperature variation on delay on SWCNT

bundle interconnect.



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Multilevel CMOS LDO-Voltage Circuit With Bi-CMOS LDO

With and Without Amplifier

Kamlesh Sharma1, Gajendra Sujediya

2, Abdul Naim Khan

3*

1,2Rajasthan Institute of Engineering & Technology, Jaipur, India

3Jaipur National University, Jaipur, India

ABSTRACT An amplifier is a device that is use to amplify the signal strength. There are lots of amplifiers

that can do other task besides amplifying. An amplifier is basically increasing the power level

of signals. We can use this principal to make building block of radio system. The signals that

we actually amplify in radio system are not necessarily sine wave, but sometimes they are.

Here we are amplifying sine wave of AC voltage or current. In this paper, the purpose is on

setting up a CMOS LDO (Low Drop Out) voltage circuit that can deliver significant voltage

drop & regulated voltage at multi-level ports that can enable SOC or NOC which have only

single power supply along with single power distribution circuit.

Keywords: CMOS, low dropout, NoC, SoC, voltage regulator

INTRODUCTION

Complementary Metal Oxide

Semiconductor (CMOS) is the

semiconductor technology used in the

transistors that are manufactured in to

most of today's computer microchips.

Semiconductors are made of silicon and

germanium, materials which "in some

way" conduct electricity, but not much

more.[1]

LDOs (Low dropout regulators)

are a simple inexpensive way to regulate

an output voltage that is to be powered

from a higher voltage input. They are easy

to design with and use. For most of the

applications, the parameters in an LDO

(Low dropout regulators) datasheet are

usually very easy to understand. Although,

the other applications require the designer

to study the datasheet more closely to

check whether or not the LDO is suitable

for the specific circuit conditions.[2]

Unfortunately, datasheets can’t present all

the parameters under all possible operating

conditions. The designer must interpret

and extrapolate the obtained information to

check the performance under non-

specified conditions.

LITERATURE REVIEW

In this paper, a CMOS without capacitor

LDO controller, which utilizing an

unobtrusive inclination circuit and a huge

number rate upgrade circuit, is planned.

These papers introduced an approach to

uproot the substantial outside capacitor,

yet these sans capacitor LDO controllers

experience the ill effects of unavoidable

tradeoffs between the precision and

criticism security.[3]

A low voltage, low

dropout (LDO) controller with an over

current redesign circuit is proposed in this

paper. By shaft zero following recurrence

remuneration; it can accomplish security

without ESR. It gives an over current sign

with hysteretic capacity. It comprises of a

voltage mention, a PMOS pass component,

a mistake intensifier in input design used

to initiative the pass component, security

circuits and stacking components.[4]

This

paper gives an outline of dependability



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Comparative Study of a 32 Bit Vedic Multiplier With a

Conventional Binary Multiplier

Rohan Muley*, Amrita Tuteja MIT, Ujjain, Madhya Pradesh, India

ABSTRACT

Multiplier plays a very important role in digital signal processing systems. To achieve high

speed operation, Vedic method has been adopted in VLSI technology. Multipliers using vedic

mathematics produces high evaluation results in terms of speed and device utilization. The

aim of this work is to design digital multipliers based on the idea of Vedic mathematics. In

order to implement a digital multiplier, Urdhva-tiryakbyham sutras of Vedic mathematics are

used to develop vertical and cross wise operations. After all these are digital multiplier, so

that they are implemented on FPGA board and tested through the 8 LED (s) in FPGA (Nexys

3). An implemented 32-bit Vedic multiplier has been simulated in Xilinx ISE 13.4 and

compared with a 32-bit binary multiplier.

Keywords: binary multiplier, DSP, vedic multiplier, VLSI

INTRODUCTION

In today's era more emphasis is given on

the signal processing applications in VLSI.

Since last two decades, work on Multiply

and Accumulate (MAC) have been in

order to improve the multiplication

techniques. But before to improve the

multiplication technique need to focus on

why multiplication is important factor in

arithmetic operations and what is this.

Multiplication is an important basic

function in arithmetic operations.

Multiplication-based operations such as

Multiply and Accumulate(MAC) and inner

product are among some of the repeatedly

used Computation- Intensive Arithmetic

Functions(CIAF) currently designed in

many Digital Signal Processing (DSP)

applications such as convolution, Fast

Fourier Transform (FFT), filtering and in

microprocessors in its arithmetic and logic

unit [1]. Since multiplication dominates

the execution time of many DSP

algorithms, so there is a need of high speed

multiplier. When we talk of multiplication

the first thing that strikes is

“Mathematics”.

Researchers prefer the ancient

methodology for any mathematical

application where sutras are used i.e.

“Vedic Mathematics.” Vedic Mathematics

is based on 16 sutras (aphorisms) namely

(Anurupye) Shunyamanyat, Chalana-

Kalanabyham, Ekadhikina Purvena,

Ekanyunena Purvena, Gunakasamuchyah,

Gunitasamuchyah, Nikhilam

Navatashcaramam Dashatahm,

Paraavartya Yojayet, Puranapuranabyham,

Sankalanavyavakalanabhyam,

Shesanyankena Charamena,

ShunyamSaamyasamuccaye,

Sopaantyadvayamantyam,

Urdhvatiryakbyham, Vyashtisamanstih

and Yaavadunam.[2]

Each of these sutras is used for specific

application, for example Nikhilam sutra is

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International Journal of VLSI Design and Technology (Vol 2 Issue 2)

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