VLSI-Unit 2
Transcript of VLSI-Unit 2
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A Brief History
1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments
2003 Intel Pentium 4 mprocessor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years No other technology has grown so fast so long
Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society
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Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
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VLSI Applications
VLSI is an implementation technology for electronic circuitry - analog or
digital
It is concerned with forming a pattern of interconnected switches and
gates on the surface of a crystal of semiconductor
Microprocessors personal computers
microcontrollers
Memory - DRAM / SRAM
Special Purpose Processors - ASICS (CD players, DSP applications)
Optical Switches
Has made highly sophisticated control systems mass-producible and
therefore cheap
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Invention of the Transistor
Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable
1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs
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Semiconductors and Doping
Adding trace amounts of certain materials to semiconductorsalters the crystal structure and can change their electricalproperties in particular it can change the number of free electrons or holes
N-Type
semiconductor has free electrons dopant is (typically) phosphorus, arsenic, antimony
P-Type semiconductor has free holes
dopant is (typically) boron, indium, gallium
Dopants are usually implanted into the semiconductor usingImplant Technology
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1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit mProc
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Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Year
Transistors
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
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MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg
< 0
(b)
+-
0 < Vg
< Vt
depletion region
(c)
+-
Vg
> Vt
depletion region
inversion region
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Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg Vs
Vgd = Vg Vd
Vds = Vd Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
nMOS body is grounded. First assume source is 0 too.
Three regions of operation Cutoff
Linear
Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+-
+
-
+
-
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nMOS Cutoff
No channel
Ids = 0
+-
Vgs
= 0
n+ n+
+-
Vgd
p-type body
b
g
s d
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nMOS Linear
Channel forms
Current flows from d to s
e- from s to d
Ids increases with Vds
Similar to linear resistor
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
= Vgs
+-
Vgs
> Vt
n+ n+
+-
Vgs > Vgd > Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
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nMOS Saturation
Channel pinches off
Ids independent of Vds
We say current saturates Similar to current source
+-
Vgs
> Vt
n+ n+
+-
Vgd
< Vt
Vds > Vgs-Vt
p-type body
b
g
s d Ids
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pMOS Transistor
Similar, but doping and voltages reversed
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
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Power Supply Voltage
GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
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Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to
drain
g
s
d
g = 0
s
dg = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFFON
ONOFF
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I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?
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Channel Charge
MOS structure looks like parallel plate
capacitor while operating in inversion
Gate oxide channel
Qchannel =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide(good insulator,
ox= 3.9)
polysilicon
gate
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Channel Charge
MOS structure looks like parallel plate
capacitor while operating in inversion
Gate oxide channel
Qchannel = CV
C =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide(good insulator,
ox= 3.9)
polysilicon
gate
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Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Qchannel
= CV
C = Cg = oxWL/tox = CoxWL
V =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide(good insulator,
ox= 3.9)
polysilicon
gate
Cox = ox/ tox
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Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Qchannel
= CV
C = Cg = oxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide(good insulator,
ox= 3.9)
polysilicon
gate
Cox = ox/ tox
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Carrier velocity
Charge is carried by e-
Carrier velocity vproportional to lateral E-field
between source and drain
v=
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Carrier velocity
Charge is carried by e-
Carrier velocity vproportional to lateral E-field
between source and drain
v= mE m called mobility
E =
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Carrier velocity
Charge is carried by e-
Carrier velocity vproportional to lateral E-field
between source and drain
v= mE m called mobility
E = Vds/L
Time for carrier to cross channel: t=
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Carrier velocity
Charge is carried by e-
Carrier velocity vproportional to lateral E-field
between source and drain
v= mE m called mobility
E = Vds/L
Time for carrier to cross channel: t= L / v
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nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time teach carrier takes to cross
dsI
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nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time teach carrier takes to crosschannel
dsQI
t
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nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time teach carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
t
W VC V V V
LV
V V V
m
ox=
WC
L m
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nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
dsI
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nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
2dsat
ds gs t dsat
V I V V V
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nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
2
2
2
dsatds gs t dsat
gs t
V I V V V
V V
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nMOS I-V Summary
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
V I V V V V V
V V V V
Shockley1st order transistor models
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pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility mp is determined by holes
Thus pMOS must be wider to provide same
current
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Channel Length Modulation
Reverse-biased p-n junctions form adepletion region
Region between n and p with no carriers
Width of depletion Ld region grows with reversebias
Leff= L Ld
Shorter Leffgives more current
Ids increases with Vds Even in saturation
n+
p
GateSource Drain
bulk Si
n+
VDDGND VDD
GND
LL
eff
Depletion Region
Width: Ld
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Chan Length Mod I-V
l = channel length modulation coefficient not feature size
Empirically fit to I-V characteristics
2
12
ds gs t ds I V V V
l
Ids
(mA)
Vds0 0.3 0.6 0.9 1.2 1.5 1.8
100
200
300
400
Vgs
= 0.6
Vgs
= 0.9
Vgs
= 1.2
Vgs
= 1.5
Vgs
= 1.8
0
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CMOS DC Response
DC Response: Vout vs. Vin for a gate
Ex: Inverter
When Vin = 0 -> Vout = VDD
When Vin = VDD -> Vout = 0
In between, Vout depends on
transistor size and current
By KCL, must settle such thatIdsn = |Idsp|
We could solve equations
Idsn
Idsp V
out
VDD
Vin
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Transistor Operation
Current depends on region of transistor
behavior
For what Vin and Vout are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
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nMOS Operation
Cutoff Linear Saturated
Vgsn < Vgsn >
Vdsn
Vdsn >
Idsn
Idsp Vout
VDD
Vin
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nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn Vtn
Vgsn > Vtn
Vdsn > Vgsn
Vtn
Idsn
Idsp Vout
VDD
Vin
Vgsn = VinVdsn = Vout
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nMOS Operation
Cutoff Linear Saturated
Vgsn < VtnVin < Vtn
Vgsn > VtnVin > Vtn
Vdsn < Vgsn
VtnVout < Vin - Vtn
Vgsn > VtnVin > Vtn
Vdsn > Vgsn
VtnVout > Vin - Vtn
Idsn
Idsp Vout
VDD
Vin
Vgsn
= Vin
Vdsn = Vout
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pMOS Operation
Cutoff Linear Saturated
Vgsp > Vgsp
Vgsp Vgsp Vtp
Vgsp < Vtp
Vdsp < Vgsp Vtp
Idsn
Idsp Vout
VDD
Vin
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pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp Vtp
Vgsp < Vtp
Vdsp < Vgsp Vtp
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDDVdsp = Vout - VDD
Vtp
< 0
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pMOS Operation
Cutoff Linear Saturated
Vgsp > VtpVin > VDD + Vtp
Vgsp < VtpVin < VDD + Vtp
Vdsp > Vgsp
VtpVout > Vin - Vtp
Vgsp < VtpVin < VDD + Vtp
Vdsp < Vgsp
VtpVout < Vin - Vtp
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDDVdsp = Vout - VDD
Vtp
< 0
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I-V Characteristics
Make pMOS is wider than nMOS such that n= p
Vgsn5
Vgsn4
Vgsn3
Vgsn2
Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0
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Current vs. Vout, Vin
Vin5
Vin4
Vin3
Vin2V
in1
Vin0
Vin1
Vin2
Vin3V
in4
Idsn
, |Idsp
|
Vout
VDD
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Load Line Analysis
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |Idsp
|
Vout
VDD
For a given Vin:
Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in
Idsn
Idsp Vout
VDD
Vin
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Load Line Analysis
Vin0
Vin0
Idsn
, |Idsp
|
Vout
VDD
Vin = 0
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Load Line Analysis
Vin1
Vin1I
dsn, |I
dsp|
Vout
VDD
Vin = 0.2VDD
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Load Line Analysis
Vin2
Vin2
Idsn
, |Idsp
|
Vout
VDD
Vin = 0.4VDD
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Load Line Analysis
Vin3
Vin3
Idsn
, |Idsp
|
Vout
VDD
Vin = 0.6VDD
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Load Line Analysis
Vin4
Vin4
Idsn
, |Idsp
|
Vout
VDD
Vin = 0.8VDD
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Load Line Analysis
Vin5
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |Idsp
|
Vout
VDD
Vin = VDD
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Load Line Summary
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn
,|Idsp
|
Vout
VDD
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DC Transfer Curve
Transcribe points onto Vin vs. Vout plot
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Vout
VDD
CV
out
0
Vin
VDD
VDD
A B
DE
Vtn VDD /2 VDD+Vtp
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Operating Regions
Revisit transistor operating regions
CV
out
0
Vin
VDD
VDD
A B
DE
Vtn VDD /2 VDD+Vtp
Region nMOS pMOS
A
B
C
D
E
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Operating Regions
Revisit transistor operating regions
CV
out
0
Vin
VDD
VDD
A B
DE
Vtn VDD /2 VDD+Vtp
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
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Noise Margins
How much noise can a gate input see before it
does not recognize the input?
IndeterminateRegion
NML
NMH
Input CharacteristicsOutput Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical HighInput Range
Logical LowInput Range
Logical HighOutput Range
Logical LowOutput Range