Advanced VLSI Design

Homework No.2

Implementing an 8-bit Adder/Subtractor.

Nima Afraz

900767858

Kazem Farjami nejhad

900767726

a. Write RTL description in Verilog or VHDL.

First of all we must findout a suitable schematic for the 8-bit

Adder/Subtractor.

This one seems good:

Now a Vhdl code is required:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity addsub is

port(A,B : in std_logic_vector(7 downto 0);

OPER: in std_logic;

RES : out std_logic_vector(7 downto 0));

end addsub;

architecture archi of addsub is

begin

RES <= A + B when OPER='0'

else A - B;

end archi;

It’s time to compile the Vhdl code:

Now testing the code with inputs :

a=0000011b=00000001opr=0 (add)

a=0000011 b=00000001 opr=1 (sub)

It work’s

b.Synthesize it using Leonardo Spectrum

In this section after producing the Vhdl file we opened Leonardo and loading

the ams600 library file we choose that in technology tab.

Read vhdl code from the source:

Now write it in an edf file:

Successful:

A report from the required gates :

Now the edf file is ready to be used in L-Edit.

c. Generate std-cell layout of it using L-Edit 8.5.

For getting started for designing in L-Edit first of all from this path

Tools>SPR>Place & Route open setup and in the first field address the

ams600.tdb and in the second field address the edf file exported from Leonardo.

The Now clicks on run and wait for the layout to show up.

Layout is ready: