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A Quarter -AnnualMagazine by VLSI Egypt

Haytham Ashour

Vice President

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9

Editorial WordWelcome to VLSI Egypt magazine

Best of CES 2012Gigabit Home Networkusing plastic optical fiber

Japan EDA Insight (1)T-Engine

Diamond is the new siliconFPGA-911

1 0

1 4

1 7

1 8

Editorial Team

Hussein Ali

Ahmad Sadek

Mohamed Atef

Website

www.vlsiegypt.com

2 ISSUE 2

The realization of an RF PLL at frequencies from58.32 to 64.8 GHz is very challenging, especiallyfor the VCO and the first frequency divider stage.

60 GHz TransceiverExamples22

VLSI-Egypt is a non-profit, service oriented,community based NGO

Contacts

magazine@vlsiegypt.com

60 GHz OperationTo Enable Gbps Wireless Communication

4

Ahmad Ibrahim

Editor in Chief

Khaled Khalaf

Ahmad Abou El-Saoud

Muhammad Zanaty

Khaled Kabil

Mahmoud Nassar

60 GHz TransceiverExamples22

Editorial Word

3ISSUE 2

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After the introduction of the first issue of the magazine we were eager to

know impression about it. We opened many channels to collect feedback

and monitor the response and see the impact of it. We found that the first

issue of the magazine was successful enough to give us the sign that we

should continue and make the second issue. Work actually didn’t stop since

then and we formulated an editorial group of volunteers who collaborated

together to make this issue.

First of all, VLSI-Egypt moderation committee would like to say that we are

proud that VLSI-Egypt Magazine is started now to run as an independent

project within VLSI-Egypt Organization by a dedicated editorial group who

we believe are able to make this issue better than the first one in many as-

pects.

We would like to express our great gratitude to VLSI Egypt Magazine edit-

orial group for working on this issue. We know that they spent a lot of time

planning, organizing, discussing, preparing and reviewing all work needed

for this issue to see the light. They did all of that for nothing but feeling the

responsibility toward the VLSI community in Egypt and the wellness to

share information and experience with all ofus.

We would also like to thank all the authors from outside the editorial group

who had participated in this issue by their valuable articles that we hope it

would have a great impact on the VLSI community in Egypt. Also, we en-

courage all those interested in writing articles, whether business or technic-

al, to contact the editorial group and we would be more than happy to

answer all your questions.

This issue of VLSI-Egypt Magazine covers the aspects of Multi-Gigabit cir-

cuits, systems and networks in three different articles. We also provide a

quick glimpse on the world of ubiquitous computing in Japan as well as the

use of Diamond for tranistors. We also start a new series about the basics of

FPGA design.

We hope you like this issue and you find it up to your expectations. We

would also like to ask you for all your feedback as your opinions had been

the main benchmark we had been using to asses our success in achieving

our goals. Finally, we would like to thank you for keeping VLSI-Egypt such a

vibrant community.

Welcome to VLSI Egypt magazine

Technical

60 GHz operation to enableGbps wireless communicationBy: Khaled Khalaf

o one can imagine carrying a laptop or any other portable device which is notconnected to the internet, or even to a local network, from which you’retransmitting and receiving information. These can be ranging from simple

text information to streaming video data that requires large data rates of fewgigabits per second. Wireless communication at 60 GHz is claimed to be the mostappropriate way to achieve the huge demands for the next generation consumerapplications.

DefinitionThe unlicensed band centered at 60GHz lies in the extremely

high frequency (EHF) band, which is the highest radio fre-

quency band according to the International Telecommunica-

tion Union (ITU), running the range between 30 and 300GHz

[1 ] . This frequency range is equivalent to wavelengths

between 10mm to 1mm in free space. That is why it is also

called the millimeter-wave (mm-wave) band. The Institute of

Electrical and Electronics Engineers (IEEE) has another fre-

quency band nomenclature that assigns 60GHz to the V band.

The V band includes frequencies ranging from 40 to 75GHz

[2] .

MotivationThe increasing demands of society for technology driven ap-

pliances are pushing the trend to shift operation to higher fre-

quencies, and the advancement in silicon technology makes

this shift feasible. Data transmission is the current example of

our choice. Communication rates of few gigabits per second

are already available in consumer applications, which is a

challenge to be supported by wireless channels. An example is

shown in Figure 1 . According to the current HDTV standard,

up to 5.6 Gbps is required for TV display with a resolution of

1920x1080, 90 Hz frame rate and 30 bits per channel per pixel.

Even higher data rates are expected to be available in the fu-

4 ISSUE 2

ture. If such data rates are to be con-

sidered for wireless transmission, large

bandwidths are required, which are

available at higher frequencies.

60 GHz band allocationsSeveral regulatory bodies in different

countries started from 2000 to allocate

unlicensed frequency bands around 60

GHz for the use of commercial

products. As shown in Figure 2, typic-

ally 7 GHz (from 5 to 9 GHz) are avail-

able for wireless communication around

60 GHz. Following band allocations,

several efforts to standardize commu-

nication over the available band were

done by standardization organizations,

resulting in standards such as

IEEE802.15.3c [4] , ECMA 387 [5] ,

WirelessHD [6] , WiGig [7] and

IEEE802.11ad [8] . These standards split

the 60 GHz band into four channels,

with around 2 GHz each. Several digital

modulations for different modes of op-

eration are also defined for different ap-

plications, reaching data rates up to

around 25 Gbps and transmission dis-

tances up to around 10 meters.

BeamformingNatural spatial isolation caused by

propagation loss due to free space path

loss (FSPL) and oxygen absorption

makes communication in this frequency

band only viable over short ranges (till

10 meters). FSPL can be calculated in its

simple form using the following equa-

tion:

FSPL(dB) = 20log(distance) + 20log

(frequency) – 147.55

This shows around 88 dB loss for 60

GHz signal at 10 m. Figure 3 illustrates

the oxygen absorption peak in the

60GHz region.

One advantage of the implicit attenu-

ation and limited range of operation at

60GHz is the possibility of bandwidth

reuse in two close offices. Directional

propagation is used to enhance signal

transmission and reception. In the

transmitter, radiated power is concen-

Fig.1 Data rate requirements for different resolutions, frame rates, and numbersof bits per channel per pixel for HDTV standard [3] .

Fig.2: Worldwide spectrumavailability in the 60 GHz band [7] .

Fig.3: Atmospheric propagation attenuation versus frequency [9] .

5ISSUE 2

trated towards the receiver instead of

being wasted in unwanted directions.

Similarly, gain is boosted in one direc-

tion and unwanted interferers can be

spatially attenuated in the receiver. This

suggests using multiple antennas at the

transmitter, to direct and enhance signal

transmission, and at the receiver, to im-

prove the sensitivity and reduce inter-

ference. The size of an antenna is

inversely proportional to the operating

frequency. For example, 60GHz opera-

tion allows the use of 16-element an-

tenna array that occupies the same area

as a dipole antenna at 5GHz [10] .

Beamforming is a signal processing

technique used in sensor arrays for dir-

ectional signal transmission or recep-

tion [11 ] . The term beamforming is

derived from spatial filters that were de-

signed to form pencil beams (Figure 4)

[12] . As shown in Figure 5, an array of

antennas with variable gain and phase

shifting (or time delay elements) can

form different antenna patterns, one of

which is a beam with a specific radi-

ation angle θ [10] . Time delays among

different antenna paths need to be com-

pensated by true time delay elements for

coherent signal combination [13] . As-

suming no channel bonding, signal

bandwidth is around 2GHz, which is

very small compared to the 60GHz car-

rier frequency. In narrowband systems,

phase shift blocks can be used instead of

true time delay elements as an approx-

imation for the multi-path signal to add

constructively [13] .

Beamforming implementationchallengesPhase shifting in a receiver can be im-

plemented in four different ways: at RF

after the LNA, at baseband after the

mixer, in the LO path or using signal

processing in the digital domain [15] .

Signal combination in the digital do-

main uses the most hardware and is the

most power hungry because the whole

front-end is copied as many times as the

number of antenna paths. Phase shifting

at RF places lossy elements directly after

the LNA which degrades the system

gain, noise figure and bandwidth. Sys-

tem gain and noise figure are less sens-

itive to amplitude variations in the large

LO signal. Thus, phase shifting at LO

provides the lowest effect on signal

quality. Phase shifting after the mixer

Fig.4: Radiation pattern of a beamformer [14] .

Fig.5: Beamforming system with antenna arrays and transceivers [10] .

6 ISSUE 2

causes insignificant deterioration of

gain and noise figure (as compared to

phase shifting at RF). Signal combina-

tion is performed at baseband in both

LO and baseband phase shifting. In

both cases, in order to avoid using mul-

tiple PLLs, LO signal should be distrib-

uted to different antenna paths. This

includes other problems, such as cross-

talk and low LO power levels.

System architectureOne antenna path of a direct conversion

60 GHz receiver is shown in the block

diagram of Figure 6. After the receiving

antenna, the receiver includes I/Q

QVCO, LNA and I/Q mixers in the

font-end. Phase shifting and signal-

combination are performed at baseband

together with LPFs, VGAs and ADCs.

In a full system, the digital output signal

is then processed in the DSP. The trans-

mitter architecture uses similar system

blocks, with the LNA and ADC are re-

placed by the PA and DAC, respectively.

Enabling technologyIn a mixed-signal chip that includes

analog and digital circuits, CMOS tech-

nology is preferred over bipolar for large

volume applications, where the digital

part dominates. Moore’s law states that

on-chip density of transistors doubles

every two years. This doubling is due to

the fabrication of transistors with smal-

ler minimum length. Smaller size tran-

sistors enable operation at higher

frequencies. That’s the reason for which

operation at mm-wave became possible

nowadays after it was just a dream years

ago.

Scaling also has drawbacks. Smaller

transistors usually require lower supply

voltage due to the lower gate oxide. For

example, the breakdown voltage is 1 .8V

for 0.18µm devices and 1 .2V for 0.13µm

ones [16] . This reduces the available

voltage headroom, and thus, decreases

voltage swings. The reduced supply

voltage also limits the number of

stacked transistors between supply and

ground terminals. Smaller size transist-

ors have more mismatch. This is be-

cause transistor mismatch is inversely

proportional to the square root of its

area according to the following equa-

tion:

where AVT is a technology constant (for

example, AVT = 5 mVµm for NMOS

device in 65nm technology).

Although devices are smaller in size, al-

lowing for higher frequency operation,

interconnects are not scalable as a con-

sequence. Taking 60GHz as an example,

wavelength in free space is 5mm. As-

suming that the effective dielectric con-

stant of a microstrip line is 4, the

on-chip wavelength at 60GHz becomes

2.5mm. This means that a track length

of more than 2500µm carrying a signal

with frequency components of 60GHz

will cause a considerable difference in

signal characteristics. This suggests the

use of electromagnetic wave simulators,

such as Agilent ADS [18] or Ansoft

HFSS [19] , to model relatively long in-

terconnects with the help of a parasitic

extraction tools, such as Mentor Graph-

Fig.7: 60GHz potential applications [7] .

Fig.6: 60GHz receiver architecture.

7ISSUE 2

ics Caliber [20] or Cadence Assura [21 ] ,

for medium and short interconnects.

Current and future applications

The large bandwidth allocated for the

60GHz frequency band could be used to

transfer tens of gigabytes of data in few

seconds. Short range indoor applica-

tions like broadband internet access and

high speed point-to-point wireless com-

munication could utilize this capability.

The only wide-spread available product

in the market that utilizes the 60 GHz

frequency band is a one port kit to re-

place the HDMI cable in HDTV con-

nections. Other products including 60

GHz Home Cinema projectors are com-

ing into market. The coming effective

target application is to embed 60 GHz

operation in WiFi. 802.11 wireless

routers will have additional great capab-

ilities when using the large 60 GHz band

together with the 2.4 and 5 GHz ones.

802.11ad wireless standard is expected

to be finalized in 2012, with the expect-

ations to be employed in commercial

wireless routers.

Figure 7 gathers the main 60 GHz usage

models, ranging from peer-to-peer high

data rate communications to a complete

home wireless high definition network

between electronic devices.

References[1 ] International Telecommunication

Union. [Online] . http://www.itu.int/

[2] IEEE Std 521-2002, IEEE Standard

Letter Designations for Radar-Fre-

quency Bands, 2003.

[3] Su-Khiong (SK) Yong, Pengfei Xia

and Alberto Valdes Garcia, 60 GHz

Technology for Gbps WLAN and

WPAN: From Theory to Practice, John

Wiley & Sons, 2011 .

[4] IEEE Std 802.15.3c-2009, Wireless

MAC and PHY Specifications for High

Rate WPANs, Oct. 2009.

[5] "Standard ECMA-387 – High Rate

60GHz PHY, MAC and HDMI PAL,"

ECMA International, Dec. 2008.

[6] “WirelessHD Specification Version

1 .1 Overview”, WirelessHD, May 2010.

[7] “Defining the Future of Multi-Gig-

abit Wireless Communications”, WiGig,

July 2010.

[8] Status of project IEEE802.11ad. ht-

tp://www.ieee802.org/11/Re-

ports/tgad_update.htm

[9] Eino Kivisaari, 60 GHz MMW Ap-

plications, Helsinki University of Tech-

nology, Telecommunications and

Multimedia Laboratory, Apr. 9, 2003.

http://www.tml.tkk.fi/Opinnot/T-

109.551/2003/kalvot/60GHz.ppt

[10] Ali M. Niknejad and Hossein

Hashemi, mm-Wave Silicon Techno-

logy: 60 GHz and Beyond, Springer,

2008.

[11 ] Wikipedia, Beamforming. ht-

tp://en.wikipedia.org/wiki/Beamform-

ing

[12] B.D. Van Veen and K.M. Buckley,

"Beamforming: A Versatile Approach to

Spatial Filtering," IEEE ASSP Magazine,

vol.5, no.2, pp.4-24, Apr. 1988.

[13] Dixian Zhao, 60 GHz Beamform-

ing Transmitter Design for Pulse Dop-

pler Radar, M.Sc. thesis, Delft

University ofTechnology, Feb. 2009.

[14] J. Bass, E. Rodriguez, J. Finnigan,

C. McPheeters, Beamforming Basics,

Connexions Web site, Jul. 27, 2005. ht-

tp://cnx.org/content/m12563/latest/

[15] Karen Scheir, CMOS Building

Blocks for 60 GHz Phased-Array Re-

ceivers, Ph.D. thesis, Vrije Universiteit

Brussel, Dec. 2009.

[16] John R. Long, RF Integrated Circuit

Design, TU-Delft MSc. course lecture

notes, 2009.

[17] M.J.M. Pelgrom, A.C.J. Duinmaijer

and A.P.G. Welbers, "Matching Proper-

ties of MOS Transistors," IEEE J. Solid-

State Circuits, vol.24, no.5, pp.1433-

1440, Oct. 1989.

[18] Advanced Design System (ADS),

Agilent Technologies.

http://www.agilent.com/find/eesof-ads

[19] HFSS, Ansoft.

http://www.an-

soft.com/products/hf/hfss/

[20] Software for IC Design and Circuit

Design Verification, Mentor Graphics.

http://www.mentor.com/products/ic_n-

anometer_design/

[21 ] Assura Physical Verification.

http://www.ca-

dence.com/products/mfg/apv/

Khaled Khalaf

Millimeter-wave researcher at imec

PhD student at VUB

8 ISSUE 2

Editors' ChoiceBest of CES 2012Sonyericcsson SmartWatchCheck out Facebook™ posts. Catch up on tweets, texts and

Email. See who's calling. Or escape with some tunes.

Discover SmartWatch. An Android™ watch with a scratch

& splash-proof multi-touch display. Clip it on. Wear it

with any 20mm wristband. Enjoy your favourite

SmartWatch apps. It's up to you.

LightPadConnected with a smartphone, The LightPad™ provides

virtually all functions of a notebook computer for an

individual. This is mainly thanks to a rebirth of rear

projection using a pico-projector. The high gain and high

contrast rear projection screen provides for a high quality

display.

ATC Mini Action CameraThe ATC Mini Action Camera is a super lightweight,

compact, waterproof and rugged action camera suitable

for the toughest of conditions. The camera records at 720P

HD video and can plunge to depths of 20 meters making it

suitable for all your on-land, off-land and even

underwater activities.

VLSI Egypt Corner

9ISSUE 2

Toward Gigabit Home NetworkUsing Plastic optical Fiber

he increasing demand for broadband services raises the need for a highbandwidth link, which should extend from the terminals to the customer’spremises. In-building networks presently are using a wide range of

transmission media: coaxial copper cables, twisted copper pair cables, free-spaceinfrared links, wireless local area network (LAN) links, etc. Each of these networks isoptimized for a particular set of services; this complicates the introduction of newservices and the creation of links between services (such as between video and dataservices). A single broadband multi-services network could provide an efficientsolution to host and connect all existing and upcoming services together.

T

The target for data rate (DR) delivered

in home could be up to 1Gbit/s in case

of fiber to the home (FTTH) or up to

120Mbit/s in case of very high bit rate

digital subscriber line (VDSL2)

technology. The home network must

not represent a bottleneck for the

expected evolution for services such as

the introduction of high definition

quality internet protocol television

(IPTV), multi-room/multi-vision

configuration and high quality video

communication via the TV set. The

home network can be used, for example,

to share multimedia contents not

necessarily delivered in real time by

access network, this content can be

stored in a device inside the house and

use it afterwards [11 ] .

At present, twisted pair and coaxial

cables are used as the physical medium

to deliver telecom services within the

customer’s premises. These two

transmission mediums suffer from

serious shortcomings when they are

considered to serve the increasing

demand for broad-band services. For

instance, twisted pair has a limited

bandwidth and it is susceptible to

electromagnetic interference (EMI).

Coaxial cable offers a large bandwidth,

but it poses practical problems due to its

thickness and the effort required to

make a reliable connection. Moreover,

the coaxial cable is not immune to EMI.

Optical fiber is extensively used for

long-distance data transmission and it

represents an alternative for

transmission at the customer premises

10 ISSUE 2

By: Mohamed Atef

as well optical fiber connections offer

complete immunity to EMI [2] . Glass

optical fibers (GOF), however, are not

suitable for use within the customer

premises because of the requirement of

precise handling, and thus, the high

costs involved. On the other hand, it is

important to have very simple and low-

cost solutions. Also the enormous

capacity of the single-mode GOF is

never necessary in this short distance

application. The Poly-Methyl-

Methacrylate Plastic Optical Fiber

(PMMA-POF) is an excellent candidate

for implementing such a short distance

network.

Certain users find that POF systems

provide benefits compared to GOF and

copper wire, which include: simpler

and less expensive components,

operation in the visible range (the

transmission windows are 530nm,

570nm, and 650nm), greater flexibility

and resilience to bending, shock and

vibration, ease in handling and

connecting (standard step-index POF

core diameters are 1mm compared with

8–100µm for glass), use of simple and

inexpensive test equipment. Finally,

POF transceivers require less power

than copper transceivers. These

advantages make POF very attractive for

use within in-building networks,

industrial control and automotive fields

as depicted in Figure 1 [3] .

The main disadvantage of the PMMA-

POF is its high transmission loss

(150dB/km at 650nm and less than

90dB/km at 530nm and 570nm) which

limits the use of PMMA plastic fibers

for transmitting light to less than 100m.

Most cheap commercial POFs have a

uniform, or step index of refraction that

is the same across the width of the fiber,

and step-index fibers (SI-POF) have the

lowest bandwidth among multimode

fibers [3] . This small bandwidth limits

the maximum data rate (DR) which can

be transmitted through POF.

To overcome the problem of POF high

transmission loss, very sensitive

receivers must be used to increase the

transmitted length over PMMA POF.

The SI-POF limited bandwidth problem

can be decreased by using multilevel

signaling like Multilevel Pulse

Amplitude Modulation (M-PAM), see

Figure 2, and Qudrature Amplitude

Modulation (M-QAM). Also the DR

can be increased more with the limited

POF bandwidth by using spectral

efficient modulation techniques like

Discrete Multi Tone (DMT) [4,5,6,7] .

Fig.1 Main POF applications

Figure 2 Multilevel pulse amplitude modulation (M-PAM)

11ISSUE 2

Pre-equalization for the light source and

post-equalization techniques can be

used to equalize for the SI-POF small

bandwidth [8,9,10] . Pre-equalizing of

light source (peaking) lowers the light

source modulation depth; this reduces

the actual power per pulse compared to

rectangular pulses without peaking.

This is at the expense of system power

budget. Post equalizer introduces

additional noise and a higher optical

power is needed to achieve the required

sensitivity. It follows that the use of pre-

or post-equalization methods are of

particular interest in systems that have

adequate power reserves. Also, for a

fixed equalization if the frequency

response changes, as a result of different

lengths of the POF or a bend in the

fiber, the result will be too much or too

little compensation and the bit error

rate (BER) will increase.

Today on the market several suppliers

offer PMMA POF media converter

solutions at 100 Mbit/s. With such

performance SI-POF may be used in the

home to interconnect all devices usually

communicating through Fast Ethernet

interfaces; for example the link between

the home gateway and the Set Top

Boxes (STB). The standard

requirements for 100 Mbit/s and 1Gbit/s

PMMA SI-POF systems introduced by

The European Telecommunications

Standards Institute (ETSI) are illustrated

in Table 1 .

For multilevel modulation, there is a

need for an integrated optical receiver

with a good performance. The optical

receiver used with multilevel signaling

must deliver a linear response over a

large input optical power range. This

leads to a more sophisticated design of

the automatic gain control (AGC)

compared to the conventional binary

receivers, where a significant part of the

large dynamic range is achieved by a

simple limiting amplifier [11 ,12] .

To receive the multilevel optical signal

we need a high linearity optical receiver

with multilevel signal, the use of the

conventional optical receivers (with

limiting amplifier) will not be useful.

The use of conventional optical

receivers with limiting amplifiers will

result in a distorted output signal with

unequal voltage levels. This makes the

signal decoding very hard or even

impossible. In the design of the

multilevel signaling optical receiver a

linear optical receiver (no limiting

amplifiers) will be considered to have

equally spaced output signal voltage

levels. Also a linear AGC is needed to

have a constant output voltage over

wide input optical power. This equally

spaced output signal voltage levels will

ease the decision levels selection for

signal decoding from multilevel signal

to the original binary signal.

For many applications it is desirable to

integrate the photodiode (PD) with a

transimpedance amplifier (TIA) into the

same chip. Placing the TIA adjacent to

the PD improves the performance by

reducing lead capacitance and

sensitivity to interference, thereby

giving higher speed and lower noise. A

further advantage of the integration of

PD with TIA is the reduction in the

external circuitry required. Hence

overall cost and PCB board size can be

reduced.

Figure 3 Media converter [13]

Table 1 ETSI for 100 Mbit/s and 1Gbit/s PMMA POF systems

12 ISSUE 2

Figure 3 shows the general block

diagram of the media converter. Both

laser diode and fully integrated optical

receiver were mounted in a plastic

optical clamp. The laser diode is driven

with a commercial IC. The integrated

optical receiver (A3PICs) consists of an

integrated transimpedance amplifier

with an integrated 400μm diameter

photodiode, limiting amplifier and line

driver on a single chip. The use of high

performance fully integrated optical

receiver enables the media converter to

reach data rate of 1Gbit/s over 50m SI-

POF.

References

[1 ] “ETSI TS 105 175-1 V1 .1 .1 (2010-

01),”

http://www.etsi.org/WebSite/homepage.

aspx, January 2010.

[2] I. Mollers, , D. Jager, R. Gaudino, A.

Nocivelli, H. Kragl, O. Ziemann, N.

Weber, T. Koonen, C. Lezzi, A.

Bluschke, and S. Randel, “Plastic Optical

Fiber Technology for Reliable Home

Networking: Overview and Results of

the EU Project POF-ALL,” IEEE

Communications Magazine, vol. 47 no.

8, pp. 58–68, 2009.

[3]P. Polishuk, “Plastic Optical Fibers

Branch Out,” IEEE Communications

Magazine, vol. Volume: 44, Issue: 9, pp.

140–148, September 2006.

[4]R. Gaudino, E. Capello, G. Perrone,

G. Perrone, M. Chiaberge, P. Francia,

and G. Botto, “Advanced Modulation

Format for High Speed Transmission

over Standard SI-POF Using DSP/FPGA

Platforms,” POF Conference 2004,

Nuerberg, pp. 98–105, September 2004.

[5] F. Breyer, S. Lee, S. Randel, and N.

Hanik, “PAM-4 Signalling for Gigabit

Transmission over Standard Step-Index

Plastic Optical Fibre Using Light

Emitting Diodes,” 34th European

Conference and Exhibition on Optical

Communication (ECOC 2008),

Brussels, Belgium, vol. 3, pp. 81–82,

September 2008.

[6] S. C. J. Lee, F. Breyer, D. Cardenas, S.

Randel, and A. M. J. Koonen, “Real-

Time Gigabit DMT Transmission over

Plastic Optical Fibre,” Electronics

Letters, vol. 45 ,no. 25, pp. 1342–1343,

2009.

[7] S. C. J. Lee, F. Breyer, S. Randel,

R.Gaudino, G. Bosco, A. Bluschke, M.

Matthews, P. Rietzsch, H. P. A. van den

Boom, and A. M. J. Koonen, “Discrete

Multitone Modulation for Maximizing

Transmission Rate in Step-Index Plastic

Optical Fibers,” Journal of Lightwave

Technology, vol. 27, no. 11 , pp.

1503–1513, June 2009.

[8]O. Ziemann, L. Giehmann, P. E.

Zamzow, H. Steinberg, and D. Tu,

“Potential of PMMA Based SI-POF for

Gbps Transmission in Automotive

Applications,” the 9th International POF

Conference, Cambridge, pp. 44–48,

October 2000.

[9] F. Breyer, N. Hanik, S. Randel, and B.

Spinnler, “Investigations on Electronic

Equalization for Step-Index Polymer

Optical Fiber Systems,” Proceedings

Symposium IEEE/LEOS Benelux

Chapter, Eindhoven, pp. 149–152,

November/December 2006.

[10]F. Breyer, S. Lee, S. Randel, and N.

Hanik, “500-Mbit/s Transmission over

50 m Standard 1-mm Step-Index

Polymer Optical Fiber using PAM4-

Modulation and Simple Equalization

Schemes,” Proc. ePhoton One Summer

School , Brest, France, July 2007.

[11 ]M. Atef, R. Swoboda, H.

Zimmermann, An Integrated Optical

Receiver for 2.5Gbit/s Using 4-PAM

Signaling, The 22nd International

Conference on Microelectronic

(ICM2010), Cairo, Egypt, 2010.

[12]M.Atef, R.Swoboda,

H.Zimmermann, Optical receiver front-

end for multilevel signalling, Electronics

Letters Journal, January 2009.

[13] Olef Zieman, POF-Plus Handbook,

Handbook of the European POF-PLUS

Project 2008 - 2011 , 2011 .

Dr. Mohamed Atef

Assistant Prof. Electrical Eng. Dept. ,

Assiut Univerity, Egypt.

moh_atef@aun.edu.eg

13ISSUE 2

JapanEDAInsight (1)

T-Engine – Steering the UbiquitousComputing World in JapanThroughout my experience studyingand living in Japan for over than fiveyears, I had the opportunity to meetwith many colleagues working in thefield of EDA whether in famous com-panies or in Universities, and togetherwith my humble Japanese language, thathelped me a lot to break the culture bar-rier/shock that any middle-east foreign-er pass through when he lives in afar-east country like China, Korea or Ja-pan with these amazing 10,000 Kanjicharacters. I managed to build a solidknowledge base of many ideas and tech-nologies influencing and driving the Ja-

panese community that I would like toshare with you in a series of articleswhich I write from the perspective of anEDA engineer. So I chose the name “Ja-pan EDA” as a title, and because thesearticles actually open the door for morereading and analysis, I complementedthe title with the word “insight” meaninga piece of Information. The topics wouldvary from the Educational System inUniversities, Research Organizations,Design Tools, Hardware Platforms, andmany other EDA trends, which I trulyhope that VLSI-Egypt magazine readersfind useful and interesting.

By: Muhammad Abdel­Salam

State of the Art

14 ISSUE 2

Prof. Ken Sakamura is a Japanese pro-

fessor in Information science at the Uni-

versity of Tokyo. He is the creator of the

Real-Time Operating System architec-

ture TRON. As of 2006, Prof. Sakamura

started the ubiquitous networking

laboratory (UNL), located in Gotanda,

Tokyo as well as the T-Engine forum for

consumer electronics which contains

many Japanese companies and I was ac-

tually a member of representing my

University. The joint goal of Ubiquitous

Networking specification and the T-En-

gine forum, is to enable any everyday

device to broadcast and receive inform-

ation as shown in the use model of Fig-

ure 1 . In this article, I would present the

T-Engine development kit and in the

following article, I would present more

about its applications that I experienced

in Ubiquitous-Japan.

T-Engine Development Kit is an open

platform for embedded system develop-

ment offered as a total complete package

with H/W, S/W, and a development en-

vironment. T-Engine consists of three

boards: CPU, LCD, and debug boards,

as shown in Figure 2 and internal archi-

tecture is shown in Figure 3. The CPU

board mounts an SH7727 SoC

(SH3/DSP core) from Renesas Techno-

logy (There are actually different ver-

sions/series of T-Engine if you explore

more at http://www.t-engine.org/), in-

ternal clock 96 MHz/external clock 48

MHz, 8 MB flash memory, 32 MB

SDRAM, CF card interface, USB host,

PCMCIA interface, sound generator

chip, 2-channel serial interfaces to

which one channel is connected to the

host PC for debugging and download-

ing the application S/W, power supply

controller, and a Real Time clock (RTC).

The LCD board mounts a touch panel

interface, infrared remote control photo

acceptance unit, and a Key SW {SW1,

SW2, SW3}. The LCD panel is 240(H) x

320(V), 262,144 colors and it is con-

trolled by an SH7727 on-chip LCD con-

troller (LCDC). The CPU board has a

bus expansion slot to which a debugger

board is connected. The debugger board

is used mainly in our experiment to cal-

ibrate the embedded S/W running on T-

Engine using a JTAG (ICE) debugger for

(SH3/DSP) core connected via a JTAG

connector.

JTAG (Joint Test Action Group, IEEE

Standard 1149.1 and IEEE Standard Test

Access Port and Boundary Scan Archi-

tecture) was originally designed for

boundary scan. It allows read/write in-

ternal registers via limited number of

Fig.1 Ubiquitous Computing Applications

15ISSUE 2

pins (typically 5 pins). It is now becom-

ing popular to use JTAG interface and

use DCU (Debug control Unit) inside

the CPU. JTAG ICE provide very basic

debug feature such as run-control,

memory/register view/edit, download,

etc.

When developing applications on this

platform, we typically write it in C/C++

and link it with the T-Kernel RTOS,

other middle ware, device drivers, and

GUI widget components and use Part-

ner-J/SH, a JTAG ICE from Kyoto Mi-

cro-Computer, together with H-UDI

(Hitachi user-debugging interface) sup-

ported by the SH7727, to perform on-

chip debugging. The H-UDI is a serial

interface which is compatible with JTAG

specifications. The JTAG debugger is

accompanied with S/W debugger pro-

gram to monitor program execution,

and perform real-time trace.

Dr. Muhammad Abdel-Salam

Technical Lead,

Mentor Graphics Emulation Division

(MED)

Fig.3 T-Engine SH7727 Architecture

Fig.2 T-Engine Development Kit

Fig.4 Developing Applications on T-Engine

16 ISSUE 2

For almost 60 years now, Silicon has

been the crowned king for semicon-

ductors industry. It all started in 1954

when the first Transistor was invented

by Texas Instruments [1 ] .It enabled the

avalanche of a great revolution in the

electronics industry with minichips, mi-

crochips and IC’s.

Year by year scientists managed to pro-

duce smaller, cheaper, more functional-

ities and increased capacity of

transistors by unit area, now as we ap-

proach the final barriers of progress

where heat dissipation is becoming an

imminent barrier , a major change is

needed [2] .

It seem that diamond the hardest

known material on earth will soon be-

comes the most used element in elec-

tronic devices. Diamond can be used as

a semiconductor, which is something

not globally known.

It was by 1952 when scientists noticed

that blue diamond shows semiconduct-

ors P-type conductivity behavior, due to

the natural impurities inside it. Since

this time it was proven that diamond

could be used in electronic circuits

manufacturing but the main barrier was

the problem of manufacturing the dia-

mond itself [3] .

Naturally made diamond is produced

when carbon buried in High Pres-

sure/High Temperature (HP/HT) medi-

um for hundreds of years but with the

current technologies, such effects can be

simulated to produce synthetic dia-

monds in the matter ofmonths.

With the current advances and the us-

age of enhanced methods such as

“Chemical Vapour Deposition”

(CVD)[4] , the manufacturing process of

artificial diamonds is becoming much

feasible, which in return opens the way

for different diamond usage that wasn’t

acceptable before due to the cost and

uniqueness of each diamond piece.

As the manufacturing process of artifi-

cial diamonds becomes more economic

and much faster, the financial barrier is

becoming smaller on using diamonds in

electronic applications.

Diamond has few properties that could

make it very lucrative option such as:

1 - Its ability to disperse heat and con-

duct it 5 times faster than normal con-

ductive/semi conductive materials.

2- Has the highest density per atoms,

which allows 1 cm of diamond to with-

stand 10 million EV.

3- Extreme resistance against shock,

pressure, radiation and even acid.

All of this could play an important role

in high processing devices “i.e server

farms”. A big problem arises with the in-

crease demand on processing power is

the heat barrier and the need for more

power-hungry cooling systems however,

with diamond this problem is going to

be minimized.

For long time the major diamond deal-

ers considered the synthetic diamond as

an enemy to their market share but now

with the current technology advances,

they decided to work by the motto say-

ing, “if you can't beat them, join them.”.

Recently, De Beers a huge multinational

company in the field ofnatural diamond

has decided to extend it’s business do-

main into the huge industry of com-

puter chips by investing millions of

dollars in starting a patner company

named Element Six , that would spe-

cialize in manufacturing synthetic dia-

monds and exploring it’s potential usage

in power microwave electronics indus-

tries [5] .

Currently, research groups around the

world are racing to produce the first

diamond based commercial electronic

devices “i.e. Diodes, Transistors and

switches” [6] [7] .

For some time now, diamond have been

used in high duty applications such as

drilling heads in petroleum industry or

in laser optics application and now is

the time for making use of its near per-

fect electrical characteristics for another

revolution in the electronics industry.

References

[1 ]http://en.wikipedia.org/wiki/Transist

or

[2] .http://www.pbs.org/wgbh/nova/tech

/digital-diamonds-au.html

[3]http://www.semi1source.com/notes/v

iewfile.asp?Which=85

[4]http://en.wikipedia.org/wiki/Chemic

al_vapor_deposition

[5]http://www.investmentu.com/2011/D

ecember/synthetic-diamonds-to-

replace-silicon-in-microchips.html

[6]http://www.youtube.com/watch?v=h

mhxX4JI3Uw

[7]http://www.aist.go.jp/aist_e/latest_res

earch/2005/20050615/20050615.html

Ahmed Sadek

Research Assistant at Nile University

Information Security Department

Ahmed.Sadek@nileu.edu.eg

Diamond is thenew SiliconBy: Ahmad Sadek

State of the Art

17ISSUE 2

FPGA 9-1-1By: Muhammad Abdel­Ghany

FPGAs or field programmablegate arrays are an attractive solu-tion for many design challenges.The adoption of FPGA in newerdesigns is increasing rapidly andit's significantly compared tonumber of successful new ASICdesigns and the total growth insemiconductors market.

In this series we will try to get youthrough successful design withFPGAs while will highlight differ-ent design methodologies andguidelines to help you efficientlyuse FPGA in your next design.

Technical

18 ISSUE 2

Market for Standard Cell ASICs, ASSPs, and Programmable LogicIBS, Inc., “System IC Market Trends” (Q2/2010 Global System IC

Industry Service), August 2010

ProgrammabilityFPGA or field programmable gate array

is a programmable device just like tradi-

tional microcontrollers and processors.

A designer just needs to translate his

design requirements into chunks of

code segments, integrate them, simulate,

debug, compile and then download to

the device to test or run the design.

The difference between a MCU and FP-

GA is "what is programmable?" MCU is

a fixed structure that can execute a fixed

set of pre-defined operations (instruc-

tions). Designer needs to translate his

design into a list of those operations ex-

ecuted in a way to implement the re-

quired behavior of the design. It's the

order of those operations and the flow

of data that differentiate one design

from another and do the required job.

Unlike MCU, FPGA has a program-

mable structure. The idea is to be able to

alter what the hardware can do not what

the hardware should do.

MCU built to be as generic as possible

to cover a range of applications possibil-

ities. One can split all MCU available in

the market into different categories ac-

cording to the applications that those

controllers are best fit. A vendor of

MCU cannot meet the requirements of

all market segments in a single device.

Some of market segments require a su-

per performance while others need

MCU with minimum power consump-

tion or the cheapest MCU. All or some

of those requirements can conflict with

each other and this is why it's im-

possible to have a single MCU that can

do everything and everywhere. In the

market a MCU that targeting industrial

applications can totally differ than a

MCU that targeting telecommunication

industry. The difference can reach the

whole architecture not only a set of

peripherals.

The main drawback of this is that de-

signers need to learn many and different

design environments, processors archi-

tectures, debugging and verification

tools, software libraries, operating sys-

tems, etc. Even if designer is not shifting

his or her job in different market seg-

ments, he or she may need to learn new

tools and processor architecture for a

new design in the same market seg-

ment. This leads to reducing ROI and

increasing time to market.

FPGA made to solve such issues and

many other issues in embedded system

designs using regular MCU.

MethodologiesDesign with FPGA is basically a kind of

digital logic design. The designer needs

to translate his architecture into a mix of

state machines, logic circuits, memories,

registers, etc. which requires good un-

derstand of underlying architecture of

FPGA.

Some of FPGA design methodologies

adopted higher level of abstraction in

which the designer can model the sys-

tem using high level languages like

Matlab or C or even using a graphical

model. Then a specialized compiler can

translate this model to a synthesizable

RTL code. This methodology was first

defined as Electronic System Level

(ESL) design by Gartner Dataquest, a

EDA-industry-analysis firm, on Febru-

ary 1 , 2001 .

ESL mainly depends on a set of pre-

designed library of primitive models

like RAMs, ROMs, shift registers, pro-

cessors, state machines, encoders, de-

coders, math functions, etc. The

designer should utilize those primitives

in his design with limited configuration

possibilities. The final results mainly

depend on the capabilities of the com-

piler to merge down this model to the

minimum set of FPGA primitive slices.

ESL methodology still not adopted in

wide scale in the industry as it not giv-

ing the optimum results of profession-

ally hand-written code.

Even if you are happy with the results of

ESL based tools, you still need to take

the decision of which FPGA to use in a

certain design. Selecting a device for a

design depends on the understanding of

your design requirements, possible fu-Fig.1 ASICs, Microcontrollers, and FPGAs

Functional Comparison

19ISSUE 2

ture updates and features, and how this

will translate to the infrastructure of a

FPGA device. Again you need to master

the device architecture and learn how

specific device architecture can fit with

your design requirements.

The good news that newer generations

of FPGA are mostly built on the same

technology but differ in terms of per-

formance, cost, pin count, and resources

count. An example of this is the 7th

series of Xilinx FPGAs. This will reduce

the time selecting a device for every new

design.

StructureFPGA have a programmable structure.

In the heart of this structure is pro-

grammable interconnection matrix and

configurable logic slices. This program-

mable structure is surrounded by pro-

grammable input/output blocks.

Understanding this structure and its

capabilities will help you to effectively

translate your design to a synthesizable

logic on this structure. Unlike ASIC

design, in FPGA you are limited to the

capabilities of the configurable logic

cells and the interconnection between

them. You cannot pack a bigger logic

circuit in a physical location than the

configurable blocks can handle.

This is one cause of performance de-

gradation in FPGA designs over similar

ASIC designs. For instance a simple de-

coder circuit can run much faster in

ASIC implementation than FPGA im-

plementation, why?

AnswerInside configurable logic blocks there

are programmable Look-Up Tables or

LUT. LUT is the primary method to

implement Boolean functions in FPGA.

We can consider LUT as single bit

ROM. The depth of that ROM depends

on number of possible inputs to LUT.

Today's FPGAs are based on 4 or 6 in-

put LUT technology. 4-input LUT can

implement any 4 input Boolean func-

tion. See figure 5 for example.

So what is the case if we need 5-input

Boolean function?

Fig.2 Example ofESL design flow using commercial design package fromBinachip, Inc.

Fig.3 FPGA Structure.

Fig.4 Example ofConfigurable LogicCell.

20 ISSUE 2

As we can see in Figure 6, increasing

the width of input enforces the synthes-

izer to split the function into multiple

LUTs and then combine those using ad-

ditional LUTs or multiplexers.

Every LUT has an intrinsic constant

delay regardless the complexity of the

function it implements. Splitting larger

functions in many LUTs creates multiple

logic levels and the total delay increases

as the number of logic level increases

too. Additional to delays in the logic

cells, there are delays in the routing

between them and this is the killing

factor in FPGA if you are seeking a

higher performance. Routing delays are

very significant especially in large logic

functions when the design must spread

over large areas of the same FPGA die.

In ASIC the situation is bit different as

wider Boolean functions can be imple-

mented using custom logic cells and

minimizing routing delays by physically

locate those cells very close on the die.

The solution to such issues is design

dependent. Some designs can adopt

pipelining in logic functions imple-

mentation breaking down the total

delay into multiple clock cycles (the

same concept of instructions pipelining

in microprocessors). In other designs we

can manually place and route logic im-

plementation in tight areas inside FP-

GA. In either of both solutions we must

first try to optimize the functions for

best implementation on FPGA.

NextIn next episodes of this series we will

introduce different FPGA features and

discuss the effective utilization of them.

We will provide valuable design tips for

those planning to use FPGA in a real

design. Also we will introduce design

methodologies in more details. We

would like to listen to your feedback

and suggestions regarding those topics

that you think we should cover in this

series.

Muhammad Abdel-Ghany

Founder & Chairman of Luxor Instru-

ments.

Fig.5 4-input Boolean function implementation in Xilinx Spartan-3E device.

Fig.6 5-input Boolean function implementation in Xilinx Spartan-3E device.

21ISSUE 2

60 GHz TransceiversExamples

Current Trends in RF and Microwave Integrated Circuits Research (2)

RFIC and microwave-IC research can bedivided into many areas such as ultralow power RF frontends, wide bandcircuits and cognitive radio design, theaim of this research it to build auniversal radio frontend, self healing RFcircuits with Built In Self Test (BIST),and millimeter-wave circuits and

systems from 30-300 GHz frequencyrange. Within this article currenttrends in millimeter-wave research areaddressed from devices performancemetrics to highly integrated radiofrontends. I t also provides some designaspects and precautions for such highfrequency circuits and systems.

By: Muhammad Elkholy

State of the Art

22 ISSUE 2

RFIC and microwave-IC research can bedivided into many areas such as ultralow power RF frontends, wide bandcircuits and cognitive radio design, theaim of this research it to build auniversal radio frontend, self healing RFcircuits with Built In Self Test (BIST),and millimeter-wave circuits and

systems from 30-300 GHz frequencyrange. Within this article currenttrends in millimeter-wave research areaddressed from devices performancemetrics to highly integrated radiofrontends. I t also provides some designaspects and precautions for such highfrequency circuits and systems.

FETs vs. HBTsBefore analyzing the two devices using

small signal models, it is important to

compare their fundamental physical

constructions shown in Fig. 1 . In field

effect transistors, the controlling charge

resides on the gate, is of opposite sign,

and is physically separated from the

controlled charge which travels through

the channel between the source and

drain. Since only one type of carriers

(electrons or holes) contributes to cur-

rent flow in the active mode of opera-

tion typically employed in HF circuits,

FETs are also described as unipolar

devices. On the contrary, in HBTs, the

controlling charge (holes in npns, elec-

trons in pnps) is collocated in the base

with the controlled charge (electrons in

npns, and holes in pnps). This explains

the bipolar nature of these devices. The

second and third main differences

between the two structures reflect the

direction of current flow, and the tech-

nological control of the minimum fea-

ture size, gate length, L, and vertical

distance between emitter and collector,

for FETs and HBTs respectively. Intrins-

ic FET speed is therefore driven by

lithography whereas HBT speed is de-

termined by the precision with which

we can grow thin semiconductor layers

vertically, for example by atomic layer

deposition techniques. Historically, ver-

tical control of semiconductor layers has

been several generations ahead of litho-

graphic resolution and less costly to

realize. However, as devices are scaled to

smaller dimensions, 3D parasitics be-

come dominant and limit real device

performance. Therefore, the most ad-

vanced HBTs and FETs require scaling

in both vertical and lateral dimensions.

All the features discussed above are

summarized in Table I.

Nanoscale MOSFETs show many bi-

polar-like features, such as gate leakage

current not unlike the base current of

the HBTs, exponential sub threshold

behavior, similar output characteristics,

and almost identical in form (although

physically different) small signal and

noise equivalent circuits. For the high

frequency circuit designer, designing

with either FETs or HBTs should be al-

most transparent.

The high frequency small signal equi-

valent circuits of both nMOS and HBT

devices is shown in Fig. 2. In the HBT at

high frequency, Cπ is dominating the

input impedance of the device and rπ

can be omitted. And this reduces the

equivalent circuit of the HBT to the

equivalent circuit of the MOS device

and one general small signal model can

be used as depicted in Fig. 3. This small

signal circuit is a good approximationFig. 1 Charge control principle in FETs and HBTs.

Table I. Comparison ofFETs and HBTs

Fig.3 general small signal equivalent circuit of both HBT and nMOS atmillimeter-wave Frequencies.

Fig.2 Small signal equivalent circuit of both MOS and HBT in high frequencies.

23ISSUE 2

for first order hand calculation and

design. Then more accurate simulation

with either BSIM 4 for CMOS or VIBIC

& HICUM models for HBTs should be

carried out for final design steps.

60 GHz Transceivers Examples60 GHz Communication Link Budget

Calculations.

Prior to presenting highly integrated 60

GHz transceivers, 60 GHz communica-

tion system link budget calculation

should be carried out. This will demon-

strate why beamforming and phased ar-

ray systems are of great interest in

millimeter-wave communication sys-

tems.

Assuming that 1 dB compression point

of the transmitter is 10 dBm and the

noise figure of the receiver is 10 dB.

Those are reasonable numbers for cur-

rent silicon technologies (90 nm

CMOS). The bandwidth is 1 GHz, this

leads to – 74 dBm noise floor of the re-

ceiver. The path loss of 60 GHz signal is

68 dB for 1 meter distance. For simple

modulation such as FSK or QPSK the

required SNR at the demodulator is

from 10 to 14 dB. Using those numbers

one can see that there is no link margin

for fading or shadowing.

One solution for this problem is using

highly directive antennas; this will en-

hance the link margin by the antenna

gain in both sides TX and RX. Highly

directive antennas are suitable for con-

sumer electronics market specially

WLAN and WPAN. Here arises the

need to develop phased-array transmit-

ters and receivers working at mm-wave

frequencies to provide high link gain

without sacrificing angular coverage.

The main advantage of the phased-ar-

rays is that electronics beamforming

and steering can be achieved. In trans-

mitters, phased-arrays are used to in-

crease the effective isotropic radiated

power (EIRP), while in receivers, they

are used to increase the signal to inter-

ference-noise ratio (SINR). Higher EI-

RP and SINR are translated into higher

bit rate and longer distance.

Phased array system can be defined as:

Multiple antenna system, electronically

change the direction of the beam, by in-

troducing a phase shift and amplitude

control for each element as shown in

Fig. 4. Assuming that the transmitter

will has 4 TX elements and the receiver

has 4 receive channels. The link budget

will increase by 18 dB (12 from TX and

6 from the RX). As a result the system

will be more robust and high distance

could be achieved.

Single Element Transceiver

Recently fully integrated 60 GHz trans-

mitter and receiver have been presented

in the literature. In this section an ex-

ample of 60 GHz transmitter and re-

ceiver will be presented. Both

transmitter and receiver are based on

sliding IF architecture, in which one

PLL or frequency synthesizer is used to

drive both RF and IF mixers. This will

eliminate the need of two local oscillat-

ors hence reducing the complexity of

the chips. Fig. 5 shows the block dia-

gram ofboth TX and RX.

In transmitter, the 48 GHz output of the

PLL is divided by 4 to generate 12 GHz

I/Q LO signal to drive the IQ modulat-

or. The differential baseband input are

fed to the modulator through baseband

VGAs. The output signal of the modu-

lator is up-converted with the Gilbert

cell mixer. The 60 GHz generated signal

is then filtered using on chip integrated

passive filter and fed to the power amp-

lifier. The purpose of the filter is to at-

tenuate both the image at 36 GHz and

the VCO feed-through at 48 GHz. A

strong feedthrough signal would affect

the linearity of the receiver frontend,

because the transmitter and receiver

antennas are placed in close proximity.

The Q-factor of integrated inductors for

the 60 GHz range is low (typically 15 to

20), resulting in high insertion loss and

limited selectivity. For a compact

design, a lumped element filter type was

chosen. The measured insertion loss is

3.3 dB at 60 GHz. The image rejection

at 36 GHz is 27.7 dB. The VCO feed-

through at 48 GHz is attenuated by 12

dB.

The saturated output power of the

power amplifier is around 20 dBm de-Fig.4 A generic beam forming system employs arrays of antennas and transceivers

to boost gain, power, and sensitivity.

24 ISSUE 2

livered to differential 100 Ω antennas. It

consists of three stages of cascode amp-

lifiers offering high gain around 30 dB

@ 60 GHz. The PA layout is drawn sym-

metrically utilizing the ac ground for the

differential signal at the symmetry line

of the layout. The matching topology

between stages is an L-C structure. The

inductances were realized as lines in the

top metal layer. They were bent in the

layout in order to end at the symmetry

axis to utilize the ac ground. The modu-

lation scheme used for data transmis-

sion is OFDM which is sensitive to

nonlinear distortion. This means that

the PA has to be optimized for high out-

put P1dB rather than for saturated out-

put power. To achieve a high P1dB, a

class A PA was chosen. The PA draws

190 mA from a 3.7 V supply. Full de-

scription and schematic of the PA is

presented in [1 ] .

The receiver exhibits the same architec-

ture; a differential architecture is adap-

ted from antenna to baseband because

of its robustness with respect to bond

wires and its common-mode rejection

ability. The quadrature LO signals for

the second down-conversion mixers are

generated by a divide-by-four circuit in

the PLL chain, which gives perfect IQ

signals because both I and Q signals re-

spond only to the rising edge of the 48

GHz VCO output.

The receiver front-end consists of a low-

noise amplifier (LNA), a mixer, a PLL

and an IF demodulator. The LNA is a

three stage common emitter amplifier

with 18 dB gain and 22 GHz bandwidth.

Its main design and implementation is-

sues have been shown in [2] . Minor

modifications have been made to the

LNA for technology and process migra-

tion. However, only the simulated over-

all noise figure was given in [2] due to

the lack of noise measurement. The 12

GHz demodulator is designed to have a

conversion gain of 50 dB with more

than 30 dB gain control range. An SPI is

introduced for the gain and IQ VGA

mismatch control, thereby reducing the

number of bond pads. The complete re-

ceiver analogue frontend has a 78 dB

conversion gain. The RX consumes 980

mW from two different supplies: 3.3

and 2.5 V.

PLL Synthesizer

The realization of an RF PLL at fre-

quencies from 58.32 to 64.8 GHz is very

challenging, especially for the VCO and

the first frequency divider stage. Using a

sliding-IF topology, the PLL frequency

is reduced to 80 percent of these values.

As a result, the following frequencies

must be generated: 46.656 GHz, 48.384

GHz, 50.112 GHz and 51 .84 GHz. If two

VCOs selectable by a digital command

are used, a VCO tuning range of

2.16×0.8=1 .728 GHz plus safety margin

is required. The feasibility of such a

solution was first shown in [3] , where

an integrated 48 GHz PLL in SiGe-BiC-

MOS with 2.4 GHz tuning range has

been demonstrated. The PLL, unlike

other TX and RX blocks, features both

bipolar and CMOS transistors. The

VCO and static dividers are realized

with bipolar transistors, while the PFD

and charge pumps employ CMOS tran-

sistors. The 48 GHz-band PLL is used to

down-convert the 60 GHz RF signals to

the 12 GHz-band. A sliding IF of about

12 GHz is generated from the 48 GHz

VCO using a 1 :4 frequency divider,

which is used for the downconversion to

baseband with an I/Q demodulator. Fig.

6 shows the basic PLL architecture sug-

gested in [5] . The VCO output fre-

quency is divided by four to generate

quadrature signals at IF of about 12

GHz. This signal is divided by the pro-

grammable divider consisting of a 1 :45

bipolar divider and a programmable

low-speed CMOS divider. The phase-

Fig.5 60 GHz TX and RX architecture

25ISSUE 2

frequency detector (PFD) compares the

9.6 MHz signal of the divided crystal

frequency with the divided VCO fre-

quency. The PFD output is connected to

a high-current charge pump (CP1) for

VCO fine tuning and a low-current

charge pump (CP2) for coarse tuning.

The two parallel tuning loops allow a

low phase noise, a low level of reference

spurs and a large tuning range to be

achieved simultaneously. The voltage di-

vider at the output of CP1 keeps the dc

voltage at the VCO fine tuning input

roughly constant [4] , which makes the

loop bandwidth fairly independent of

device parameter variations with pro-

cess, supply voltage and temperature

(PVT). The total tuning range is defined

by the slow coarse tuning loop, in which

the noise of CP2 is almost eliminated by

a large external capacitor. In this trans-

ceiver, a 48 GHz PLL as described in [2]

contains only one VCO. An IEEE com-

patible PLL using an array of two VCOs

has been tested successfully and will be

included in a future design. The meas-

ured PLL phase noise at 1 MHz offset

was -98 dBc/Hz [3] . This corresponds to

an integrated RMS phase error after

baseband filtering below 1 .5o, which is

more than sufficient for 16-QAM OF-

DM transmission [5] .

ConclusionIn this article, we presented an intro-

duction to the current research in milli-

meter wave integrated circuits. It also

illustrates the new applications in which

millimeter wave circuits and systems

can be applied. Limitation and chal-

lenges for millimeter wave design in

current silicon technologies are ad-

dressed. Finally a simple description of

one of the state of the art 60 GHz trans-

mitter and receiver is provided.

In the next articles we will focus on mil-

limeter wave phased array systems from

architecture to circuit implementation

in silicon technologies.

References[1 ] Glisic, S.; Scheytt, J.C.: A 13.5-to-17

dBm P1dB, Selective High-Gain Power

Amplifier for 60 GHz Applications in

SiGe, Bipolar/BiCMOS Circuits and

Technology Meeting (BCTM), Oct.

2008.

[2] Sun, Y.; Borngräber, J.; Herzel, F.;

Winkler, W.: A Fully Integrated 60 GHz

LNA in SiGe:C BiCMOS Technology,

Bipolar/BiCMOS Circuits and Techno-

logy Meeting (BCTM), Santa Barbara,

USA, Oct. 2005, pp. 14-17.

[3] Herzel, F.; Glisic, S.; Winkler, W.: In-

tegrated frequency synthesizer in SiGe

BiCMOS technology for 60 and 24 GHz

wireless applications, Electronics Let-

ters, 43 (2007), 154–156.

[4] Herzel, F.; Osmany, S.A.; Scheytt,

J.C.: Analytical phase-noise modeling

and charge pump optimization for frac-

tional-N PLLs. IEEE Trans. Circuits

Syst. I, Regular Papers, 57 (2010),

1914–1924

[5] Herzel, F.; Choi, C.-S.; Grass, E.:

Frequency synthesis for 60-GHz OFDM

transceivers, European Conference on

Wireless Technology (EuWiT2008),

Amsterdam, 2008, pp. 77-80.

Muhammad Aly El-Kholy

Microwave, milli-meter researcher , IHP

M.Sc Electronics and communications

Fig.6 Schematic of frequency synthesizer.

26 ISSUE 2

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