Firmware implementation ofFirmware implementation ofInteger Array SorterInteger Array Sorter

Characterization presentationCharacterization presentationDec , 2010Dec , 2010

Elad BarzilayElad Barzilay

Uri NatanzonUri Natanzon

Supervisor: Moshe PorianSupervisor: Moshe Porian

The need for HistogramsThe need for HistogramsMany image processing algorithms relay on the use Many image processing algorithms relay on the use

of histograms.of histograms.

For example - Photo “auto fix” – histogram equalizationFor example - Photo “auto fix” – histogram equalization

minmax min

fixed original

Full Dynamic RangePixel Pixel photo

Photo Photo

Photo

Min

Photo

Max

0

Full Dynamic Range

#2 bits

For example:

Project GoalsProject Goals

•Building a generic integer array sortBuilding a generic integer array sort

firmware on an FPGA board firmware on an FPGA board

•Develop a comprehensive testingDevelop a comprehensive testing

and debugging environment.and debugging environment.

Project OverviewProject OverviewSystem capabilities & requirements System capabilities & requirements

– Sorting an array of finite integers set.Sorting an array of finite integers set.– Zero latency system.Zero latency system.– Fully debug-able.Fully debug-able.– System operation via PC interface.System operation via PC interface.

Design principlesDesign principles– Generic implementation.Generic implementation.– Top down design.Top down design.– Error detection and handling.Error detection and handling.

System implementation on the DE2 evaluation card. System implementation on the DE2 evaluation card. PC GUI implementation on MATLAB.PC GUI implementation on MATLAB.Complete development process: Characterization-> Complete development process: Characterization->

debugging platform.debugging platform.

High-level overviewHigh-level overview

SpecificationsSpecifications

Data input rate: one word per clk.Data input rate: one word per clk.System outputs: sorted array, min, max, median, System outputs: sorted array, min, max, median,

average, common item.average, common item.Output starts one clock after last input word.Output starts one clock after last input word.In and out buffered UART communication with rate In and out buffered UART communication with rate

115,200 bps.115,200 bps.PLL modulated clock 50M->60M.PLL modulated clock 50M->60M.Synchronized reset.Synchronized reset.

SORT_TOP – Inputs & OutputsSORT_TOP – Inputs & OutputsTime DiagramTime Diagram

““DUDE” – Debugging Under DUDE” – Debugging Under Development EnvironmentDevelopment Environment

MATLAB based GUI for data injection, result MATLAB based GUI for data injection, result validation and status queryvalidation and status query

““DUDE” – usage modesDUDE” – usage modes

• Send user defined arrays of data to be sorted.Send user defined arrays of data to be sorted.

• Send random arrays of data to be sorted.Send random arrays of data to be sorted.

• Query and show the value of registers of the system.Query and show the value of registers of the system.

• Verify the correctness of the sorted returned data Verify the correctness of the sorted returned data array.array.

• Configure system state registers.Configure system state registers.

• Create fully user generated packets to generate errors.Create fully user generated packets to generate errors.

• View bit representation of the messages sent and View bit representation of the messages sent and received .received .

• Logging of out/in-bound messages.Logging of out/in-bound messages.

Message Pack StructureMessage Pack Structure

SOF

ID

Data Length

Data (Payload)

Data (Payload)

CRC

EOF

8 bits

1 Byte. Some constant predefined flag

1 Byte. For message tracking

2 Bytes. Specifies the length of the data segment in bytes.

1 Byte. The CRC type will be defined later.

1 Byte. Some constant predefined flag

address 1 Byte. Specifies the addressed block

address 1 Byte. Type options are : set, query, sort

[Data Length] X Bytes. (up to 65535 bytes)Holds the data and control signal to be fed into SORT_TOP

Project mile stones:29/10/10 18/11/10 8/12/10 28/12/10 17/1/11 6/2/11 26/2/11 18/3/11 7/4/11 27/4/11 17/5/11

project characterization

VHDL code

VHDL simulation

Matlab GUI

software debug

synthesis and P&R

FPGA - PC conectivity

full system debug

Mid–way

presentation

final

presentation