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Transcript of REGISTER MANAGMENT TOOL Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date:...
REGISTER MANAGMENT TOOL
Preformed by: Liat Honig
Nitzan Carmel
Supervisor: Moshe Porian
Date: 12/11/2012
Duration: Two Semesters
Final presentation – Part A
MANY TEAMS NEED TO CREATE THEIR OWN REGISTER BLOCKS FOR FPGA SYSTEMS.
LEADING TO
BUGS Double Effort
THE SOLUTION
A REGISTER MANAGEMENT TOOLAutomatically generates registers according
to a required specification using a smart interface!
INSERT YOUR PROJECT’S
SPECIFICATIONS TO THE GUI
AUTOMATICALLY CREATE VHD AND
HSID FOR REGISTER BLOCKS!
AUTOREG – A SMART REGISTER MANAGEMENT TOOL
Project Goals
o Determine and characterize a local bus for communication with all the register slave blocks.
o Generic Implementation that allows reuse in multiple projects.
o Encapsulation of implementation, which will be hidden from the user.
THE SOLUTION – A REGISTER MANAGEMENT TOOL
Creates unity in the registers VHD files
Automatically generates registers according to the required specification.
Enables REUSE
Saves money and resources
Project Goals
o Determine and characterize a local bus for communication with all the register slave blocks.
o Generic Implementation that allows reuse in multiple projects.
o Encapsulation of implementation, which will be hidden from the user.
THE SOLUTION – A REGISTER MANAGEMENT TOOL
Creates documentation for the components created Leads to an organized – HSID
Alarms in case of incorrect input
Manages the registers through the entire project
Project Goals
o Determine and characterize a local bus for communication with all the register slave blocks.
o Generic Implementation that allows reuse in multiple projects.
o Encapsulation of implementation, which will be hidden from the user.
PROJECT SPECIFICATIONS
1. Writing a GUI interface through which the user will determine a variety of attributes.
4. No special license will be needed to operate the tool, an EXE file will be given to the user.
3. VHDL: VHD filesLocal Bus
MasterSimulation
Environment
2. Interactivity - The tool will provide feedback for user errors and will provide a summary output.
5. HSID will be generated under IEEE standards (IP-XACT)
PROJECT STEPS 1. Determine the implementation platform of the user interface and data processing: Excel/MATLAB/C++/C#/JAVA .
2. Full characterization of the tool capabilities.
3. Learning the working environment (Wishbone protocol, advanced VHDL coding , MODELSIM simulation environment).
4. VHDL generic design and simulation.
5. Implementing the GUI (Graphic User Interface)
6. Implementing Automatic VHDL generation.
7. Final MODELSIM and MATLAB Simulations.
VHDL IMPLEMENTATION
Project Goals
o Determine and characterize a local bus for communication with all the register slave blocks.
o Generic Implementation that allows reuse in multiple projects.
o Encapsulation of implementation, which will be hidden from the user.
GENERAL DESCRIPTION
Block
Local Bus
Chip data I/O
Register access
Register RegisterRegister
Block
Block
Project Goals
o Determine and characterize a local bus for communication with all the register slave blocks.
o Generic Implementation that allows reuse in multiple projects.
o Encapsulation of implementation, which will be hidden from the user.
VHDL TOP ARCHITECTURE
Block_A_reg_top Function_2
Function_3
Function_1
Block A
Reg_status_1
Wis
hbone
Mast
er
Reg_enable_2
func_err_3
reset clk
o Determine and characterize a local bus for communication with all the register slave blocks.
o Generic Implementation that allows reuse in multiple projects.
o Encapsulation of implementation, which will be hidden from the user.
WB Slave
Reg1
Reg2
Reg3
Reg4
Priority Encoder
reg_chosen
4
WBMaster
Functional Block
Data from chosen register
Inputs from block
Outputs to block
Block_A_reg_top
REG BLOCK ARCHITECTURE
WISHBONE - OPEN SOURCE PROTOCOL
Block C
clk_i
cyc_i
stb_i
adr_idat_i
dat_oack_o
Stall_o
we_i Block BWB
Master
Block A
WISHBONE SLAVE COMPONENT
Idlewr_en=‘0’rd_en=‘0’
Read Cyclerd_en=‘1’
(wbs_cyc_i) ●(_ _wbs stb i )
(wbs_cyc_i) ●(_ _wbs stb i )
Active Cycle
wbs_stall_o=‘1’
Write Cyclewr_en=‘1’
wbs_we_iwbs_we_i
Cycle Finishedwbs_ack_o=‘1
’
dout_validdi
n_ac
k
wbs_c
yc_i
WB Slave
gen_reg Functional Block
gen_reg Component
Idlereg_chosen=‘0
din_ack=‘0’dout_valid=‘
0’
Read action
addr==reg addr
The Register is
chosenreg_chosen=‘
1’
Write action
addr==reg addr
rd_en wr_en
addr==reg addr addr==reg addr
Invalid Read
Actiondout_valid=‘
0’
Valid ReadAction
dout_valid=‘1’
Valid Write Action
din_ack=‘1’
Invalid write
Actiondin_ack=‘0’
Register type is WRegister type is R/RW/COR/CONST
Register type is W/RW Register type is R/COR/CONST
WB Slave gen_reg Functional Block
GENERIC IMPLEMENTATION
GENERIC IMPLEMENTATION
VHDL SIMULATION
SIMULATION ENVIRONMENT
Macro Scripts
SIMULATION ENVIRONMENT
• Compilation
• Simulation• Waveforms
Test BenchMacro Scripts
SIMULATION ENVIRONMENT
Macro Scripts
• Compilation
• Simulation• Waveforms
Test Bench
• Procedure called serially many times
• Comparison to expected values
• Reporting results to output file
Waveforms
Results Output File
Simulation outputs
Simulation input
TEST PLAN - OVERVIEW
Testing small modules separately gen_reg.vhd:
Read Write Read/Write Clear On Read Const.
wbs_reg.vhd Read transactions (single/burst) Write transactions (single/burst)
encoder_generic.vhd Then, testing the entire design
Gen_block.vhd
TEST PLAN – CASES
Testing Regular Activity Various generic values for address width Various values for data Read/Write single/burst wishbone cycles for
suitable registers Testing system boundaries Testing system generics
WB slave
addr = 0010COR
addr = 1110W/R
Encoder
reg_chosen
4
WBMaster
Functional Block
.
.
.
.“00000000”
Write Request‘00001101’
“00001101”
EXAMPLES – WRITE AND READ REGISTER SIMULATION
Legal addr+ .Legal
operation= Request granted!
WB slave
addr = 0010COR
addr = 1110W/R
Encoder
Reg_chosen
4
WBMaster
Functional Block
.
.
.
.“00001101”
EXAMPLES – WRITE AND READ REGISTER SIMULATION
Legal addr+ .Legal
operation= Request granted!
WB slave
addr = 0010COR
addr = 1110W/R
Encoder
Reg_chosen
4
WBMaster
Functional Block
.
.
.
.Data from Register
EXAMPLES – WRITE AND READ REGISTER SIMULATION
SCENARIO: WB MASTER WRITES 7 THEN 8 TO REGISTER
din = 7 and then 8
wr_en = ‘1’ for 2 cycles
EXAMPLES – WRITE AND READ REGISTER SIMULATION
dout = 7 and then 8
din_ack = ‘1’ for 2 cycles
• UPDATED DATA FROM WB MASTER IS TRANSFERRED TO REGISTER• DIN_ACK RISES, INDICATING DOUT IS UPDATED• REGISTER NOT INFLUENCED BY DATA FROM BLOCK (REG_IN_B)
EXAMPLES – WRITE AND READ REGISTER SIMULATION
RESULTS – REQUEST IS LEGAL!
• SCENARIO: WB MASTER TRIES TO READ FROM THIS REGISTER’S ADDRESS (REGISTER ADDRESS IS 10)
• ALSO A LEGLAL REQUEST!
• RESULT: DOUT_VALID RISES TO ‘1’
Dout_valid = ‘1’rd_en = ‘1 ’
addr = 10
EXAMPLES – WRITE AND READ REGISTER SIMULATION
• SCENARIO: WB MASTER TRIES TO READ FROM A DIFFERENT REGISTER ADDRESS
• NOT A LEGAL REQUST!• RESULT: DOUT_VALID IS ‘0’ INDICATING
DATA IS NOT VALID FOR THE CURRENT CYCLE
Dout_valid = ‘0’
rd_en = ‘1 ’
addr = 15
EXAMPLES – WRITE AND READ REGISTER SIMULATION
EXAMPLES - CLEAR ON READ REGISTER SIMULATION
WB slave
addr = 0010COR
addr = 1110W/R
Encoder
Reg_chosen
4
Functional Block
.
.
.
.
“00000000”“00000000”
WBMaster
Register written with
‘0’
WB slave
addr = 0010COR
addr = 1110W/R
Encoder
Reg_chosen
4
WBMaster
.
.
.
.
“00010000”“00010000”
EXAMPLES - CLEAR ON READ REGISTER SIMULATION
Functional Block
Register written with
‘1’
WB slave
addr = 0010COR
addr = 1110W/R
Encoder
Reg_chosen
4
Functional Block
.
.
.
.
“00000000”“00010000”
WBMaster
EXAMPLES - CLEAR ON READ REGISTER SIMULATIONRegister is
not cleared until it is read
Block clears input
WB slave
addr = 0010COR
addr = 1110W/R
Encoder
Reg_chosen
4
Functional Block
.
.
.
.
“00000000”“00000000”
WBMaster
EXAMPLES - CLEAR ON READ REGISTER SIMULATION
Register is cleared
Register is read
GRAPHICAL USER INTERFACE
Easy to use user experience
Feedback is provided in real time
Data is filled automatically if possible
Easy project view and management
Data and Address can be represented in both Hexadecimal and Decimal formats
REQUIREMENTS FROM GUI
OPENING SCREEN – PROJECT SETTINGS
Settings made for the entire
projectChoose a protocol
Specify address widthChoose address
radixSpecify data width
Choose data radix
Specify number of blocks
Specify a directory to save the generated
files
Browser for finding the requested directory
OPENING SCREEN – PROJECT SETTINGS
Settings made for the entire
projectChoose a protocol
Specify address widthChoose address
radixSpecify data width
Choose data radix
Specify number of blocks
Specify a directory to save the generated
files
Continue to next screen
2ND SCREEN – EDIT BLOCK SETTINGS
Settings made for the specific
block
Specify a name
Provide a description (optional)
Opens text editor
2ND SCREEN – EDIT BLOCK SETTINGS
Settings made for the specific
block
Specify a name
Provide a description (optional)
Specify an initial address
Specify number of registers
choose reset polarity
back to project settings
delete current block
Continue to next screen
Navigation tree view
3RD SCREEN – EDIT REGISTER SETTINGS
Settings made for a specific
register
Specify a name
Provide a description
Choose register type
Specify the offset address
Specify the initial data value
Navigation tree view
Back to block
settings
delete current register
3RD SCREEN – EDIT REGISTER SETTINGS
Settings made for a specific
register
Specify a name
Provide a description
Choose register type
Specify the offset address
Specify the initial data value
TOP MENUS File menu
Help menu
Create a new projectOpen an existing
projectSave project as
Save current projectClose current project
Exit AutoReg
About AutoRegOpen user guide
Generate menu
Generate VHDL filesReport for errors
TREE VIEW
“Top View” of the entire project
Automatically sorted by the
absolute address
Allows easy navigation
between all the screens and
components
Addresses and names are filled
automatically
Navigation is blocked when
errors or missing data is found
in the current window
TREE VIEW
Easy to use user experience
Data is filled automatically if possible
Easy project view and management
ERRORS DISPLAYAutoReg notifies the user and prevents access to some contents in the project whenever:
Data isn’t legal/valid/complete
Addresses/bits are
overlapping
Before Deleting an object
2. Addresses and data must be positive numbers within the user-determined range
1. Names must be valid VHDL names
3. Some necessary inputs is missing or invalid data was inserted
ERRORS DISPLAYAutoReg notifies the user and prevents access to some contents in the project whenever:
Data isn’t legal/valid/complete
Addresses/bits are
overlapping
Before Deleting an object
2. Bits defined under “Special bits” must not overlap
1. Addresses/ names must not overlap
ERRORS DISPLAYAutoReg notifies the user and prevents access to some contents in the project whenever:
Data isn’t legal/valid/complete
Addresses/bits are
overlapping
Before Deleting an object
2. User is prompt “Are you sure?” before deleting a block or a register
1. User is prompt to save changes before exiting the project
ERRORS DISPLAYAutoReg notifies the user and prevents access to some contents in the project whenever:
Data isn’t legal/valid/complete
Addresses/bits are
overlapping
Before Deleting an object
In part B of the project – a conclusive report before generating the VHDL code
Easy to use user experience
Feedback is provided in real time
CONCLUSIONS
VHDL:
Problem: during the simulation ( of a read cycle) we saw an unexpected glitch.
Observation: the simulator works in series (and not in parallel).This caused unexpected behavior and the glitch to appear.
Solution: using a macro file instead of a TB for this simulation showed there wasn’t a glitch at all!
DEBUG , SOLUTIONS AND CONCLUSIONS
GUI:
Problem: as the GUI developed , we had to duplicate a lot of code for the different screens and functions of the GUI, resulting in a “pumped” code.
Solution: Moving some of the duplicated code into side-functions that made the code more readable and easy to maintain. Later in the project we used more side functions in advance which proved to be a good decision.
DEBUG , SOLUTIONS AND CONCLUSIONS
DEBUG , SOLUTIONS AND CONCLUSIONS GUI:
Problem: The requirements from the GUI changed frequently through the work, causing many code re-writes and need to perform wide changes to the program and patch-like code.
Conclusion: Plan the details in advance.
PLAN FOR PART B
1. Creating a conclusive report that will show up at the
end of the GUI.
2. Programing the Generation of VHDL files out of the
GUI inputs
3. Creating an HSID for the registers with IP-XACT
format XML.
4. Performing initial synthesis.
SCHEDULE FOR PART B
Due Date Task
20.11.12 Creating a conclusive report
1.1.13 Creating an HSID with IP-XACT format XML
1.2.13 Generation of VHDL
1.2.13-1.3.13 Exams
15.3.13 Initial synthesis
15.4.13 Project Document and Final Presentation
DEMO:// . . / ? = 3http www youtube com watch v U GVYfzikq
M
SUGGESTIONS FOR A LATER PROJECT
1. An option to create a wide register (more than one
address).
2. Support other protocols (not wishbone only)
3. Support more register types
4. Add a possibility to mix between the bits of the same
register when it comes to access manners.
5. Support boards and not just on FPGA
6. Search and filter possibilities
7. Copy-Paste possibilities
SUGGESTIONS FOR A LATER PROJECT
8. Creating a database with options to import and
export
9. An option to duplicate , add or delete a register using
a right-click option from the tree view.
10. Unifying the edit_block figure and the edit_reg
figure to prevent window from “jumping”
11. Under the help menu, add a keyboard map for all
keyboard shortcuts of the GUI.
THE END