LZRW3 Decompressor dual semester project Part A Mid Presentation Students: Peleg Rosen Tal Czeizler...

LZRW3 Decompressordual semester project

Part A Mid Presentation

Students:Peleg RosenTal Czeizler

Advisors:Moshe PorianNetanel Yamin

22.6.2014

Presentation Content• Project Goals• Project Requirements• Algorithm Overview• Project Top Block Diagram• Decompression Core Top View• Decompression Core Design and Data Flow• Stages Overview• Problems and Solutions• Project Schedule and Gantt

Project Goals

Project Goals• Implementation of LZRW3 data decompression core.

• Implementation of LZRW3 data decompression core.

• Implementation of a verification environment.

Project Goals

Project Requirements

Project RequirementsPart A:

• Core Requirements:– Process data at the speed of 1 Gbps.– Support data blocks with output of 2KB – 32KB.– Relay only on the FPGA’s internal memory.– VHDL Implementation.

Part A:


• Full simulation environment (golden model and checkers).


Part A:



Part B:

• Synthesis & implementation of FPGA device (Xilinx Virtex-5).


Part A:



Part B:

• Synthesis & implementation of FPGA device (Xilinx Virtex-5).

• GUI implementation in VisualStudio.


Output item (Copy item): [slot address , length ] In this case Output item = [ , ]

BABDACABDBCAA21 30 3

LZRW3 compression algorithm

Hash Function

Hash Table

ABD

Slot address

1

Slot address

4 5 6

Slot address

BAB

0

ABD

Slot address

Send every 3 literals to the hash function

Put offset in the hash table

If the slot is occupied and the literals match - make copy item

6

Structure

Algorithm Overview

StructureFile header (8 byte)

Algorithm Overview

StructureFile header (8 byte)Groups:

Algorithm Overview

StructureFile header (8 byte)Groups: - control bytes (2 bytes)

Algorithm Overview

StructureFile header (8 byte)Groups: - control bytes (2 bytes) - data bytes (16 - 32 bytes)* The last group might be smaller

Algorithm Overview

File headerDecode the header to determine the file size and whether it is compressed or not.

Algorithm Overview

Control bytesDecode control bytes to determine the position and type of the items in the group, and where the next control bytes are.

Algorithm Overview

Literal itemsWrite as is to output file.

Algorithm Overview

Copy itemsDecode to determine the offset and length of a literal sequence to be copied to the output file.

Algorithm Overview

Copy itemsDecode to determine the offset and length of a literal sequence.Write from the output memory to itself accordingly.

Algorithm Overview

Project Top Block DiagramWM-

1

WS-3WM-

3

WS-2

WS-1

WM-2

LZRW3DECOMPRESSION

CORE

Decompression Core Top view

DECOMPRESSION CORE

Decompression Core Design and Data Flow

COREDATA IN

5 BYTES BUFFER SELECT

HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE

CORE MANAGEMENT STAGE

5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE

ADDRESS MANAGERSTAGE

OUTPUT MAMORYSTAGE

HASHTABLE

HASH TABLE SELECTLZRW3 GO

DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

Stages Overview – Core Management Unit

Core Management Unit• Goals:

• To communicate with the core's periphery.

• To receive the input data and parse it.

• To transmit the appropriate control signals to the next stages.

• Method:

• The unit starts with ‘clear’ mode, which initializes the core.

• The following 10 clock cycles are dedicated to Header and Control Bytes decoding.

• From this point on, the unit determines the Mode and sets the appropriate

controls according to the current byte and the previous 4 bytes.

Core Management Unit – Mode selection

Core Management Unit – Outputs

Stages Overview – 5 Bytes Buffer

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

BUSY

New byte (8)

Mid byte (8)

Old byte (8)

Older byte (8)

Oldest byte (8)

Five Bytes BufferNew byte (8)

NewByte

Register

MidByte

Register

OldByte

Register

Older Byte

Register

Oldest Byte

Register

Stages Overview – Hash Function

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

BUSY

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

Stages Overview – Hash Function

#3 Hash Function StageTABLE INDEX = (((40543*(((*(PTR))<<8)^((*((PTR)+1))<<4)^(*((PTR)+2))))>>4) & 0xFFF)

PTR pointes to the first byte . TABLE INDEX range: 0 to 4095.

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 7 2 6 1 5 0 4 3 7 2 6 1 5 0 4 3 2 1 0

, ,0000,0000

0000, , ,0000

0000,0000, ,

, , , , , , , , , , , , , , ,

a a a a a a a a

b b b b b b bb

c c c c c c c c

a a a a a b a b a b a b b c b c b c b c c c c c

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

Stages Overview – Hash Table Stage

Block Overview – Write Address Counter

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

Write Address Counter

According to Mode signal: • For Literal items increments by 1.• For Copy items increments by Length.• Else, doesn’t increment.

Block Overview – Hash Table

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

Hash Table

OFFSET

OFFSET

16 bits

4096

ro

ws

WriteAddressCounter

Offset in

Read Index (12)

Offset out

Write Index (12)

From Hash Func

From Core Mgmt

5 bitsMemory number

11 bitsMemory address

Hash TableSelect

Hash Table – Default String

OFFSET

OFFSET

16 bits

4096

ro

ws

5 bitsMemory number


The Default String

The LZRW3 algorithm dictates that the

string “123456789012345678” is set as

default.


OFFSET

OFFSET

16 bits

4096

ro

ws

5 bitsMemory number


The Default String


string “123456789012345678” is set as

default.

Meaning, when a sequence starting

“123..” is received, a copy item is

created, even if it is the first time the

sequence appears.


OFFSET

OFFSET

16 bits

4096

ro

ws

5 bitsMemory number


00000 000000000001264

The Default String


string “123456789012345678” is set as

default.

Meaning, when a sequence starting

“123..” is received, a copy item is

created, even if it is the first time the

sequence appears.

The index ‘1264’ is initialized with

zeroes, which stand for the default

string.

Block Overview – First 2 Bytes

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

Why is First 2 Bytes needed?

Why is First 2 Bytes needed?• In the original file: ABCXYZABC• In the compressed file: ABCXYZC1C2

Why is First 2 Bytes needed?• In the original file: ABCXYZABC• In the compressed file: ABCXYZC1C2

• If we wish to keep our Hash Table identical to the Hash Table of the compressor, we must somehow fetch AB instead of C1C2.

First Two Bytes

OFFSET

16 bits

4096

ro

ws

Old byte & Mid byte

Bypass Read Index (12)

Two bytes out

Write Index (12)

From Hash Func

From Core Mgmt

8 bits

First byte

8 bits

Second byte

Hash TableSelect


X

Y

Z

BA


X

Y

Z

X

Y

ZY

Z

C1

BA

INDEX


X

Y

Z

X

Y

ZY

Z

C1

INDEX

BA


X

Y

Z

X

Y

Z

Y

Z

C1

INDEX

B

A


Y

X

Z

X

Y

Z

INDEX

Y

Z

C1

INDEX

B

A


Y

X

Z

INDEX

Y

Z

C1

INDEX

B

A

INDEX


Y

X

B

A

INDEX

X

Y

Z

Y

Z

C1

A

Stages Overview – Address Manager

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

Stages Overview – Output Memory

COREDATA IN


HASHFUNC WRITE

INDEXWRITEINDEX

READINDEX

READINDEX

BYPASSREADINDEX

WRITEINDEX

HASH FUNC SELECT

5 BYTESBUFFER

OLDEST

NEW

FIRST 2BYTES

MODE

COPY LENGTH

OFFSET

WRITEADDRESSCOUNTER

MODE

COPY LENGTH

COPY 1

COPY 2

READADDRESS

MODE

MODE

MODE

COPY LENGTH

WRITEADDRESS

ADDRESSMANAGER

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT

DATA IN

MEMORY BLOCK 18

DATA OUT

COREDATA OUT

LITERAL BYTE

LITERAL BYTE


5 BYTES BUFFERSTAGE

HASH FUNC STAGE

HASH TABLE STAGE


OUTPUT MAMORYSTAGE

HASHTABLE


DATA IN VALID

EOF IN

CLIENT READY

LZRW3 DONE

DATA OUT VALID

DATA IN TAKEN OLD

MID

NEW

COPY 2

COPY 1OLD

MID

NEW

BYPASSMODE

CORE MANAGEMENT

UNIT

INDEX

NEW

OLD

MID

READADDRESS

MODE

COPY LENGTH

WRITEADDRESS

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN

DATA OUT COREDATA OUT

LITERAL BYTE

NEW BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 2

DATA IN

DATA OUT

LITERAL BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 3

DATA IN

DATA OUT

LITERAL BYTE

ADDRESSMANAGER

COPY MODE

3

2 - 25

1 - 7 2 - 7 3 - 7

3 - 25 4 - 25

DATA 2

DATA 1

DATA 3

READADDRESS

MODE

COPY LENGTH

WRITEADDRESS

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN


LITERAL BYTE

NEW BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 2

DATA IN

DATA OUT

LITERAL BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 3

DATA IN

DATA OUT

LITERAL BYTE

ADDRESSMANAGER

COPY MODE

3

2 - 25

1 - 7

2 - 7

3 - 7

3 - 25 4 - 25

DATA 2

DATA 1

DATA 3

READADDRESS

MODE

COPY LENGTH

WRITEADDRESS

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN


LITERAL BYTE

NEW BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 2

DATA IN

DATA OUT

LITERAL BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 3

DATA IN

DATA OUT

LITERAL BYTE

ADDRESSMANAGER

COPY MODE

3

1 - 7

2 - 7

3 - 7

2 - 25

3 - 25

READ ENABLE

WRITE ENABLE

WRITE ENABLE

READ ENABLE

READ ENABLE

1

2

DATA 2

DATA 1

DATA 3

READADDRESS

MODE

COPY LENGTH

WRITEADDRESS

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN


LITERAL BYTE

NEW BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 2

DATA IN

DATA OUT

LITERAL BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 3

DATA IN

DATA OUT

LITERAL BYTE

ADDRESSMANAGER

1 - 7

2 - 7

3 - 7

2 - 25

3 - 25

READ ENABLE

WRITE ENABLE

WRITE ENABLE

READ ENABLE

READ ENABLE

1

2

DATA 2

DATA 1

DATA 3

READADDRESS

MODE

COPY LENGTH

WRITEADDRESS

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 1

DATA IN


LITERAL BYTE

NEW BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 2

DATA IN

DATA OUT

LITERAL BYTE

WRITE ADDRESS

READ ADDRESS

WRITE ENABLE

READ ENABLE

WRITE ADD SELECT

MEMORY BLOCK 3

DATA IN

DATA OUT

LITERAL BYTE

ADDRESSMANAGER

2 - 25

3 - 25

WRITE ENABLE

WRITE ENABLE

DATA 2

DATA 1

Timing Considerations• The project requirements dictates clock frequency of 125 MHz.

Timing Considerations• The project requirements dictates clock frequency of 125 MHz.• Our concern was that the memory stage’s muxes will limit the frequency.

Timing Considerations• The project requirements dictates clock frequency of 125 MHz.• Our concern was that the memory stage’s muxes will limit the frequency.• After writing the VHDL code for the memory stage we synthesized it and ran a timing

analysis, which provided the following result:

Timing Considerations• The project requirements dictates clock frequency of 125 MHz.• Our concern was that the memory stage’s muxes will limit the frequency.• After writing the VHDL code for the memory stage we synthesized it and ran a timing

analysis, which provided the following result:

• Conclusion: The timing requirements will be met.

Primary vs Final Design

4 Kbyte FIFO

Hash Function

Header Decoder

Control Bytes

Decoder

Copy Item Decoder

HashTable

Write AddressCounter

Copy Counter

Output Memory

32 Kbyte

3 Byte

1 Byte

1 Byte

1 Byte

Controller

Data in

Index12 Bit

4 Bit

Index

Length

Offset in

Offset out

Data in

Read Address

FromInput Block

Data out

Fetch stage

Decode stage

Calc Address stage

Output Memory stage

1 Byte

3Byte

buffer

AddressManager

Writeaddress

Readaddress

Write Address

Write Address

To Output Block

Problems and SolutionsProblem #1: Preforming a copy procedure


In the initial design: only 1 output memory.



The problems:



The problems: - Wasting copy length clock cycles in order to copy item.



The problems: - Wasting copy length clock cycles in order to copy item.- Must stop the pipe and store the incoming data in a FIFO located at the core’s beginning while copying.



The problems: - Wasting copy length clock cycles in order to copy item.- Must stop the pipe and store the incoming data in a FIFO located at the core’s beginning while copying.- Demands a very complicated controller.




The solution:




The solution:18 different memory blocks, which enable us to preform every copy in 2 clock cycles: 1 for reading the data from all the required memories, and the second for writing the data back to the right memories. No dependency on copy length!

Problems and SolutionsProblem #2: Ignoring the Control Bytes


In the initial design: 3 bytes buffer.



The problem:



The problem: the Control Bytes are needed for the core management unit to operate correctly, but must be ignored in the data flow (they mustn't be written in the hash table, and we need to remember the preceding items). The problem was how to ignore them without losing data.




The solution:




The solution:Enlarging the buffer from 3 bytes to 5 bytes which enables us to remember the items that preceded the Control Bytes. This done, we can select the preceding items and 'bypass' the Control Bytes with the 5 bytes buffer mux.

Problems and SolutionsProblem #3: Maintaining the Hash Table Correctly


In the initial design: No First 2 Bytes memory.



The problem:



The problem: Before acting on a copy item, the first two bytes of the literal sequence represented by the copy should be concatenated with the previous literal items.




The solution:




The solution:Maintaining the First 2 bytes memory, which holds the first 2 bytes of each literal sequence whose offset is written to the hash table. This way, concatenation is possible by extracting the necessary bytes from the first 2 bytes memory.

New ProblemProblem #4: Copy adjacent to the sequence it points to


The problem:


The problem: When trying to concatenate the first 2 bytes of a copy, there is a problem if the copy item arrives straight after the literal sequence that created it. The first 2 bytes are not yet stored, thus cannot be retrieved.



The proposed solution:



The proposed solution:Comparator, which determines if the index of the copy item is the last index written to in the Hash Table. If so, the relevant data is bypassed.

Date Goals

21/3/2014 – 5/4/2014 Project Characterization &Algorithm interpreting

6/4/2014 Characterization Presentation

7/4/2014 – 2/6/2014 Full Characterization of all blocks

3/6/2014 – 21/6/2014 •System blocks VHDL •Design

22/6/2014 Mid presentation

23/6/2014 – 25/7/2014 Work on project paused for exams

Project Schedule 1/2

Date Goals

30/7/2014 – 4/9/2014 VHDL design Cont.

21/9/2014 – 20/10/2014

Building a simulation environment

21/10/2014 – 21/11/2014

Simulation run & debug

22/11/2014 Part A - Final presentation

23/11/2014 – 10/12/2014

FPGA synthesis & implementation

11/12/2014 – 25/12/2015 GUI implementation

26/12/2014 – 24/1/2015

Tests & debug

25/1/2015 Final project presentation

Project Schedule 2/2

Weeks: 0 - 5 6 – 12 13 – 19 20 - 26 27 - 32

Characterization & interpretation

Characterization presentation

Blocks characterization VHDL blocks

implementation Mid presentation Exams VHDL Cont. Building Sim Env Part A - Final pres. Sim & Debug FPGA synthesis GUI implementation Tests & debug Writing portfolio Final presentation

.........……

……………...………....

............….……………………………………………………….…….…

Project Gantt

…………………………………….…….…...……

33

22

2

24

4

2

8

4

LZRW3 Decompressor dual semester project Part A Mid Presentation Students: Peleg Rosen Tal Czeizler...

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Transcript of LZRW3 Decompressor dual semester project Part A Mid Presentation Students: Peleg Rosen Tal Czeizler...