ELEN 468 Lecture 22 1

ELEN 468Advanced Logic Design

Lecture 22Timing Verification

ELEN 468 Lecture 22 2

General

Timing verifications should be performed at every design stageTiming verifications at early stages are not accurate as no detailed physical information available

ELEN 468 Lecture 22 3

Type of Timing Paths

1. Input -> register2. Register -> register3. Register -> output4. Input -> output

Combinational Logic

Register

Combinational Logic

Combinational Logic

Register

Clock

ELEN 468 Lecture 22 4

Clock Scheduling

Register

Combinational Logic

Register

Clock

i jti tj

LD: logic delay

ELEN 468 Lecture 22 5

Timing Constraints

skewij = ti – tj <= CP – LDmax – setupmax (long path)

skewij = ti – tj >= holdmax – LDmin (short path)

tj

ti

hold

setup

LDmin

LDmax

CP

ELEN 468 Lecture 22 6

Static Timing Analysis

Arrival time: input -> output, take max Required arrival time: output -> input, take minSlack = required arrival time – arrival time

2

3

4

3

7

11

2

3

7/4/-3

5/3/-2

4/7/3

8/8/0

9/6/-3

20/17/-3

11/11/0

18/18/0

23/20/-3

ELEN 468 Lecture 22 7

False Paths

[3:5, 2:3] [3:5, 2:3] [3:5, 2:3]

Min, max rising

Min, max falling

Max path delay = 15?

ELEN 468 Lecture 22 8

Dynamically Sensitized Paths

a b

c

d

‘0’

a

b

c

d

ELEN 468 Lecture 22 9

Gate and Wire Model

C R

L rLcL/2 cL/2

r: resistance per unit length

c: capacitance per unit length

ELEN 468 Lecture 22 10

Example of Model

0 1

2

3

L1

L2

L3

C2

C3

0 1

2

3

R rL1

rL2

rL3

cL1/2

(L1+L2+L3)c/2

cL2/2+C2

cL3/2+C3

ELEN 468 Lecture 22 11

Delay Estimation

D0 = R ( C0 + C1 + C2 + C3 )

D1 = D0 + R1 ( C1 + C2 + C3 )

D2 = D1 + R2 C2

D3 = D1 + R3 C3

0 1

2

3

R R1

R2

R3

C0

C2

C3

C1

ELEN 468 Lecture 22 12

Interconnect Size Scaling

Wire width scales faster than wire height wires are thinner and tallerWires are placed closerCoupling capacitance start to dominate substrate capacitance

ELEN 468 Lecture 22 13

Crosstalk Noise

Crosstalk noise may cause Glitch and logical error Extra propagation delay

aggressor

victim

ELEN 468 Lecture 22 14

Elimination of Timing Violation

Action EffectIncrease clock period Eliminates the violation,

constrained by specifications

Reroute critical path Reduce interconnect delays

Resize and substitute devices Reduce device delays and improve setup and hold

margins

Redesign clock tree Reduce clock skew

Substitute a different algorithm Reduce path delays

Substitute architecture Reduce path delays

Pipeline/retiming Reduce path delays

Change technologies Reduce path and device delays