ELEN 468 Lecture 15 1

ELEN 468Advanced Logic Design

Lecture 15Synthesis of Language Construct I

ELEN 468 Lecture 15 2

Synthesis of Netsmodule and3( y, a, b, c

);input a, b, c;output y;wire y1;

assign y1 = a & b;assign y = y1 & c;

endmodule

module and3( y, a, b, c );input a, b, c;output y;wire y1;

assign y1 = a & b;assign y = y1 & c;

endmodule

An explicitly declared net may be eliminated in synthesisPrimary input and output (ports) are always retained in synthesisSynthesis tool will implement trireg, tri0 and tri1 nets as physical wires

ab

cy

ELEN 468 Lecture 15 3

Synthesis of Register Variables

A hardware register will be generated for a register variable when It is referenced before value is assigned in a

behavior Assigned value in an edge-sensitive behavior

and is referenced by an assignment outside the behavior

Assigned value in one clock cycle and referenced in another clock cycle

Multi-phased latches may not be supported in synthesis

ELEN 468 Lecture 15 4

Synthesis of Integers

Initially implemented as a 32-bit registerAlways specify size when declare a constant For example, parameter a = 3’b7

will consume 3 bits while default is 32 bits

ELEN 468 Lecture 15 5

Unsupported Data Types

realtimerealtimestring

ELEN 468 Lecture 15 6

Synthesis of Memories

No direct supportUsually implemented as array of registersNot efficient as external memoryMinimize the usage of such memory

ELEN 468 Lecture 15 7

Synthesis of “x” and “z”

A description that uses explicit “x” or “z” values for data selection cannot be synthesizedThe only allowed usage of “x” is in casex and casez statements The only allowed use for “z” is in constructs that imply 3-states deviceIf a UDP assigns a value of “x” to a wire or reg, it will be treated as “don’t care”

ELEN 468 Lecture 15 8

Synthesis of Arithmetic Operators

If corresponding library cell exists, an operator will be directly mapped to itSynthesis tool may select among different options in library cell, for example, when synthesize an adder

Small wordlength -> ripple-carry adder Long wordlength -> carry-look-ahead adder Need small area -> bit-serial adder

Implementation of “*” and “/” May be inefficient when both operands are variables If a multiplier or the divisor is a power of two, can be

implemented through shift register

ELEN 468 Lecture 15 9

Synthesis of Shift Operators

Synthesis tools normally support shifting by a constant number of bitsCannot support a variable shift

ELEN 468 Lecture 15 10

Relational OperatorsRelational operators ( <, >, >=, <= ) can be

implemented through Combinational logic

Adder/subtractor In bit-extended format Calculate A – B, check extended bit of result

0 -> A >= B 1 -> A < B

module compare ( lt, gt, eq, A, B );input A, B;output lt, gt, eq;

assign lt = ( A < B );assign gt = ( A > B );assign eq = ( A == B );

endmodule

module compare ( lt, gt, eq, A, B );input A, B;output lt, gt, eq;

assign lt = ( A < B );assign gt = ( A > B );assign eq = ( A == B );

endmodule

ELEN 468 Lecture 15 11

Synthesis of Identity Operators

The logical identity operators ( ==, != ) and the case identity operators ( ===, !== ) are normally synthesized to combinational logic

ELEN 468 Lecture 15 12

Reduction, Bitwise and Logical

Operators

They are translated into a set of equivalent Boolean equations and synthesized into combinational logic

ELEN 468 Lecture 15 13

Conditional Operator

The conditional operator ( ? … : ) synthesizes into library muxes or gates that implement the functionality of a muxThe expression to the left of ? is formed as control logic for the mux

ELEN 468 Lecture 15 14

Concatenation Operator

Equivalent to a logical busNo functionality of its ownGenerally supported by synthesis tool

ELEN 468 Lecture 15 15

Grouping of Operatorsmodule operator_group ( sum1, sum2, a, b,

c, d );input a, b, c, d;output sum1, sum2;

assign sum1 = a + b + c + d;assign sum2 = ( a + b ) + ( c + d );

endmodule

module operator_group ( sum1, sum2, a, b, c, d );input a, b, c, d;output sum1, sum2;

assign sum1 = a + b + c + d;assign sum2 = ( a + b ) + ( c + d );

endmodule

adder

adder

adder

sum2

adder

adder

adder

sum1

ab

c

d

ELEN 468 Lecture 15 16

Synthesis of Assignment

Support by synthesis is vendor-specificContinuous assignment can be mapped directly to combinational logicProcedural assignment, LHS must be register variableProcedural continuous assignment Supported by some tools

PCA to register cannot be overwritten by any procedural assignment

ELEN 468 Lecture 15 17

Expression Substitution in Procedural Assignmentmodule multiple_assign ( out1,

out2, a, b, c, d, sel, clk );output [4:0] out1, out2;input [3:0] a, b, c, d;input sel, clk;reg [4:0] out1, out2;

always @ ( posedge clk ) begin

out1 = a + b;out2 = out1 + c;if ( sel == 1’b0 ) out1 = out2 + d;

endendmodule

module multiple_assign ( out1, out2, a, b, c, d, sel, clk );output [4:0] out1, out2;input [3:0] a, b, c, d;input sel, clk;reg [4:0] out1, out2;

always @ ( posedge clk ) begin

out1 = a + b;out2 = out1 + c;if ( sel == 1’b0 ) out1 = out2 + d;

endendmodule

module multiple_assign ( out1, out2, a, b, c, d, sel, clk );output [4:0] out1, out2;input [3:0] a, b, c, d;input sel, clk;reg [4:0] out1, out2;

always @ ( posedge clk ) begin

out2 = a + b + c;if ( sel == 1’b0 ) out1 = a + b + c +

d;else out1 = a + b;

endendmodule

module multiple_assign ( out1, out2, a, b, c, d, sel, clk );output [4:0] out1, out2;input [3:0] a, b, c, d;input sel, clk;reg [4:0] out1, out2;

always @ ( posedge clk ) begin

out2 = a + b + c;if ( sel == 1’b0 ) out1 = a + b + c +

d;else out1 = a + b;

endendmodule

ELEN 468 Lecture 15 18

Exercise Exercise 55

ELEN 468 Lecture 15 19

Problem 2.3Write structural description with primitive gates for the Boolean equation:y1 = a0’●b2 + a2’ ●a0●b2 + a0● b1’ ●b0

module P23(y1, a0, a2, b0, b1, b2); input a0, a2, b0, b1, b2; output y1; wire not_a0, not_a2, not_b1, t1, t2, t3; not(not_a0, a0); and(t1, not_a0, b2); not(not_a2, a2); and(t2, not_a2, a0, b2); not(not_b1, b1); and(t3, a0, not_b1, b0); or(y1, t1, t2, t3);endmodule

ELEN 468 Lecture 15 20

Problem 2.4

Write Verilog code using continuous assignment for the Boolean equation:y1 =a0’●b2 + a2’ ●a0●b2 + a0● b1’ ●b0

module P23(y1, a0, a2, b0, b1, b2); input a0, a2, b0, b1, b2; output y1; assign y1= (~a0)&b2 | (~a2)&a0&b2 | (~b1)&b0;

endmodule

ELEN 468 Lecture 15 21

Problem 2.11

Using Verilog predefined primitive, write a description of the circuit below:

module p211(q, qb, set, rst); input [7:0] set, rst; output [7:0] q, qb;

nor [7:0] (q, rst, qb); nor [7:0] (qb, set, q); endmodule

ELEN 468 Lecture 15 22

Problem 2.12

Using continuous assignment, write a description of the circuit below:

module p212(q, qb, set, rst); input [7:0] set, rst; output [7:0] q, qb;

assign q=~(rst | qb); assign qb = ~(set | q);endmodule

ELEN 468 Lecture 15 23

Problem 2.21

Which of the following assignments have correct syntax? What is stored in the memory?

a. A=8’b101 0000 0101b. B=5’o9 wrongc. C=12’HAA 0000 1010 1010d. D=4’BBB wronge. E=4d’x3 wrongf. F=4’hz zzzzg. G=4’O8 wrongh. H=8’hz9 zzzz1001