ELEN 468 Lecture 231 ELEN 468 Advanced Logic Design Lecture 23 Testing.

ELEN 468 Lecture 23 1

ELEN 468Advanced Logic Design

Lecture 23Testing


Verification vs. Testing Verifies correctness of designPerformed by simulation, hardware emulation, or formal methodsPerformed prior to manufacturing

Verifies correctness of manufactured hardwareTwo-part process:

1. Test generation: software process executed once during design

2. Test application: electrical tests applied to hardware

Test application performed on every manufactured device


Why Do We Need Testing?

Properly designed chip may fail in field Transient failures – under heating, radiation … Intermittent failures – random, finite duration Permanent failures

Manufacturing defects Wafer defects Contaminated atmosphere in clean room, dust

… Impure processing gasses, water, chemicals … Photomask misalignment


Testing Levels and Implied Cost

Wafer: 0.01 – 0.1Packaged-chip: 0.1 – 1Board: 1 – 10System: 10 – 100Field: 100 – 1000


Types of Defects

Wire shortsDiscontinuous wires, may due to stress or peelingHigh resistance viasGate to source/drain junction shortThreshold voltage change


Fault ModelsWhy model faults? I/O function tests inadequate, real

defects too numerous and often not analyzable

A fault model Identifies targets for testing Makes analysis possible

Common fault models Transistor open and short faults Single stuck-at faults


Single Stuck-at FaultThree properties define a single stuck-at fault

Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate

Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

a

b

c

d

e

f

1

0

g h i 1

s-a-0j

k

z

0(1)1(0)

1

Test vector for h s-a-0 fault

Good circuit valueFaulty circuit value


Fault Equivalence and Collapsing

Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent.


Equivalence Rules

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0

sa1

sa0

sa1

sa0

sa0sa1

sa1

sa0

sa0

sa0sa1

sa1

sa1

AND

NAND

OR

NOR

WIRE

NOT

FANOUT


CheckpointsPrimary inputs and fanout branches of a combinational circuit are called checkpointsCheckpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.

Total fault sites = 16

Checkpoints ( ) = 10


Transistor (Switch) FaultsMOS transistor is considered an ideal switch and two types of faults are modeled: Stuck-open -- a single transistor is permanently

stuck in the open state Stuck-short -- a single transistor is permanently

shorted irrespective of its gate voltage

Detection of a stuck-open fault requires two vectorsDetection of a stuck-short fault requires the measurement of quiescent current (IDDQ)


Stuck-Open Example

A two-vector stuck-open testcan be constructed byordering two stuck-at tests

A two-vector stuck-open testcan be constructed byordering two stuck-at tests

A

B

VDD

C

PMOS

NMOS

Stuck-open

1

0

0

0

0 1(Z)

Good circuit states

Faulty circuit states

Vector 1: test for A s-a-0(Initialization vector)

Vector 2: (test for A s-a-1)


Stuck-Short Example

A

B

VDD

C

Stuck-short1

0

0 (X)

Good circuit state

Faulty circuit state

Test vector for A s-a-0

IDDQ path in faulty circuit


Testing Techniques

IDDQ test – detect short circuit current Test pattern generation and verify output


Test Pattern for Stuck-At Faults

abc

abc

SA1

Ygood = a●b●c

Ya-SA1 = b●c

Test pattern: {a,b,c} = 011

No need to enumerate all input combinations to detect a fault

No need to enumerate all input combinations to detect a fault


Path Justification and Sensitization

‘1’

‘1’

Test SA0Justification

Sensitization


Functional ATPG – generate complete set of tests for circuit input-output combinations

129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749,

214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years

Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE

Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ %

Automatic Test Pattern Generation (ATPG)


D-Logic

D 1 in good 0 in fault

D’ 0 in good 1 in fault

X – don’t care

In Out

0 1

1 0

X X

D D’

D’ D

Inverter


D-Algorithm

‘1’

‘1’

Test SA0

= trace back input to enable D

Monitor output in D logic


Algorithm

D-ALGPODEMFANTOPSSOCRATESWaicukauski et al.ESTTRANRecursive learningTafertshofer et al.

Est. speedup over D-ALG(normalized to D-ALG time)17232921574 ATPG System2189 ATPG System8765 ATPG System3005 ATPG System48525057

Year

1966198119831987198819901991199319951997

Algorithm Speedups


Fault SimulationFault simulation Problem Given

A circuit A sequence of test vectors A fault model

Determine Fault coverage - fraction (or percentage) of

modeled faults detected by test vectors Set of undetected faults

Motivation Determine test quality and in turn product

quality Find undetected fault targets to improve tests


Fault Coverage and Defect Level

W = 1 – Y(1-T)

W: probability of shipping a defective partY: manufacturing yieldT: fault coverage


Fault Simulator in a VLSI Design Process

Verified designnetlist

Verificationinput stimuli

Fault simulator Test vectors

Modeledfault list

Testgenerator

Testcompactor

Faultcoverage

?

Remove tested faults

Deletevectors

Add vectors

Low

Adequate

Stop


Fault Simulation ScenarioMostly single stuck-at faultsSometimes stuck-open, transition, and path-delay faultsEquivalence fault collapsing of single stuck-at faultsFault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosisFault sampling -- a random sample of faults is simulated when the circuit is large


Fault Simulation Algorithms

SerialParallelConcurrentProbabilistic


Serial Algorithm

Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault:

Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing

responses with saved responses If response differs, report fault detection and suspend

simulation of remaining vectors

Advantages: Easy to implement, less memory Most faults, including analog faults, can be simulated

Disadvantage: Much repeated computation, CPU time prohibitive for VLSI

circuits


Parallel Fault SimulationBest with two-states (0,1)Exploits inherent bit-parallelism of logic operations on computer wordsMulti-pass simulation: each pass simulates w-1 new faults, where w is the machine word lengthSpeed up over serial method ~ w-1Not suitable for circuits with timing-critical and non-Boolean logic


Parallel Fault Simulation Example

a

b c

d

e

f

g

1 1 1

1 1 1 1 0 1

1 0 1

0 0 0

1 0 1

s-a-1

s-a-0

0 0 1

c s-a-0 detected

Bit 0: fault-free circuit

Bit 1: circuit with c s-a-0

Bit 2: circuit with f s-a-1


Concurrent Fault Simulation

Event-driven simulation of fault-free circuitOnly note those parts of the faulty circuit that differ in signal states from the fault-free circuitA list per gate containing copies of the gate from all faulty circuits in which this gate differsList element contains fault ID, gate input and output valuesFaster than parallel simulationUses most memory


Concurrent Fault Simulation Example

a

b c

d

e

f

g

1

11

0

1

1

11

1

01

1 0

0

10

1

00

1

00

1

10

1

00

1

11

1

11

0

00

0

11

0

00

0

00

0 1 0 1 1 1

a0 b0 c0 e0

a0 b0

b0

c0 e0

d0

d0

g0 f1

f1


Probabilistic Fault Simulation

Identify test vectors with high toggle coverageUse them as basis for test vectorsCorrelation: toggle coverage fault coverageToggle tests are simpler


Fault SamplingA randomly selected subset (sample) of faults is simulatedMeasured coverage in the sample is used to estimate fault coverage in the entire circuit.Advantage: saving in computing resources (CPU time and memory)Disadvantage: limited data on undetected faults - hard to identify location of coverage problems


Delay Fault Testing

Half open circuitHalf short circuitFunctionality is not affectedTiming performance is degraded

ELEN 468 Lecture 231 ELEN 468 Advanced Logic Design Lecture 23 Testing.

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