COMBINATIONAL LOGIC DESIGN PRACTICES
64
COMBINATIONAL LOGIC DESIGN PRACTICES
description
COMBINATIONAL LOGIC DESIGN PRACTICES. COMBINATIONAL LOGIC DESIGN PRACTICES. DOCUMENTATION TIMING DECODERS ENCODERS THREE-STATE DEVICES MULTIPLEXERS XOR GATES AND PARITY CIRCUITS COMPARATORS. DOCUMENTATION. WHAT? SPECIFICATION: INTERFACE, FUNCTION HOW? BLOCK DIAGRAM SCHEMATIC DIAGRAM - PowerPoint PPT Presentation
Transcript of COMBINATIONAL LOGIC DESIGN PRACTICES
COMBINATIONAL LOGIC DESIGN PRACTICES
COMBINATIONAL LOGIC DESIGN PRACTICESDOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
DOCUMENTATIONWHAT?
SPECIFICATION: INTERFACE, FUNCTIONHOW?
BLOCK DIAGRAM SCHEMATIC DIAGRAM TIMING DIAGRAM STRUCTURED LOGIC DEVICE DESCRIPTION CIRCUIT DESCRIPTION
BLOCK DIAGRAMSINPUTS, OUTPUTSFUNCTIONAL MODULESDATA PATHSCONTROL SIGNALS
BLOCK DIAGRAMS
PROCESSOR
DECODINGLOGIC MEMORY
16
816
CS~
R/W
DATA
BUSCOLLECTION OF TWO OR MORE
RELATED SIGNALSSLASH AND NUMBER: NUMBER OF
SIGNALS
SIGNAL NAMESWELL CHOSEN NAMES CONVEY
INFORMATION
SIGNAL ACTIVE LEVELSACTIVE HIGHACTIVE LOWASSERTED WHEN AT THE ACTIVE
LEVELDEASSERTED (NEGATED) WHEN NOT
AT THE ACTIVE LEVEL
NAMING CONVENTIONACTIVE HIGH: GO, PAUSE, READYACTIVE LOW: GO~, PAUSE.L, /READY,
ETC.
ACTIVE LEVELS FOR PINSINVERSION BUBBLE: ACTIVE LOWNO INVERSION BUBBLE: ACTIVE
HIGH
COMBINATIONAL LOGIC DESIGN PRACTICESDOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
CIRCUIT TIMINGTIMING DIAGRAM
RELATIONSHIPS AMONG INTERNAL SIGNALS REQUIREMENTS ON EXTERNAL SIGNALS
CAUSALITYDELAY TIMING TABLEDELAYS RANGE: MINIMUM, MAXIMUM,
TYPICALPROPAGATION DELAY (tHL, tLH,…)
TIMING SPECIFICATIONSMAXIMUM: HOW DID THEY MEASURE IT?
TEMPERATURE (25 °C, 40 °C, …) CAPACITIVE LOAD (0 pF, 50 pF, …) VCC (3.3V, 5V, …)
TYPICAL IDEAL?
MINIMUM WORK FOR ZERO DELAY? TEMPERATURE, LOAD, VCC, …
TIMING ANALYSISCOMPLEX FOR LARGE CIRCUITSCAD TOOLS HELP, BUT:
NEED TO UNDERSTAND WHAT THE RESULTS ARE
OFTEN MANY CONTROLS NEED TO KNOW HOW TO TEST
COMBINATIONAL LOGIC DESIGN PRACTICESDOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
DECODERSMULTIPLE INPUT, MULTIPLE OUTPUT
CIRCUIT THAT CONVERTS CODED INPUTS TO CODED OUTPUTS
INPUT AND OUTPUT CODES ARE DIFFERENT
ONE-TO-ONE MAPPING
DECODERS
BINARY DECODERSn-TO-2n DECODERSACTIVATE EXACTLY ONE OF 2n
OUTPUTS BASED ON n-BIT INPUTS
2-TO-4 BINARY DECODER
LOGIC SYMBOLS
ONE-HALF OF 74x139 DECODER
ONE-HALF OF 74x139 DECODER
74x138 3-TO-8 DECODER
CASCADING BINARY DECODERS74x138 HAS BOTH ACTIVE HIGH AND
ACTIVE LOW ENABLE INPUTSWITH TWO 138s WE CAN ENABLE OR
THE OTHER USING THE MSB
SEVEN-SEGMENT DECODER
COMBINATIONAL LOGIC DESIGN PRACTICESDOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
ENCODERSMULTIPLE INPUT, MULTIPLE OUTPUT
CIRCUIT THAT CONVERTS CODED INPUTS TO CODED OUTPUTS
OUTPUT CODE HAS FEWER BITSONE-TO-ONE MAPPING
BINARY ENCODER2n-TO-n ENCODERINPUT: 1-OUT-OF-2n CODEOUTPUT: n-BIT BINARY CODE
BINARY ENCODER
BINARY ENCODER
Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7
PRIORITY ENCODERS
8-INPUT PRIORITY ENCODER
74x148 PRIORITY ENCODER
COMBINATIONAL LOGIC DESIGN PRACTICESDOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
THREE-STATE DEVICESENABLE - DEVICE “FLOATS”FLOATS = HIGH IMPEDANCE STATE = = HI-Z STATE = DISCONNECTED
STATE
MULTIPLE SOURCES ON THREE-STATE PARTY LINEMULTIPLE THREE-STATE DEVICES
CAN SHARE SINGLE LINEFIGHTINGDEAD TIME
MULTIPLE SOURCES ON THREE-STATE PARTY LINE
STANDARD THREE-STATE BUFFERSHYSTERESIS?BUFFERSTRANSCEIVERS
COMBINATIONAL LOGIC DESIGN PRACTICESDOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
MULTIPLEXERSDIGITAL SWITCH
MULTIPLEXERS
1
0
n
jj iDjMENiY
74x151, 74x157
74x153
THREE-STATE MUXESDISABLED OUTPUT HI-Z INSTEAD OF
0: 74x151 74x251 74x153 74x253 74x157 74x257
EXPANDING MUXESEXPAND THE NUMBER OF BITS
MULTIPLE 74x151s… FANOUTEXPAND THE NUMBER OF SOURCES
MUXES, DEMUXES, BUSES
MUXES, DEMUXES, BUSES
DECODERS AS DEMUXES
DECODERS AS DEMUXES
DESIGN EXAMPLECREATE A MUX-DEMUX SYSTEM FOR
A 2-BIT BUS4 2-BIT INPUTS TO 4 2-BIT OUTPUTSUSE STANDARD TTL CHIPS FROM
BOOK
COMBINATIONAL LOGIC DESIGN PRACTICESDOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
XOR FUNCTION
XY=X’Y + XY’
XOR MULTIGATE DESIGN
XOR MULTIGATE DESIGN
XOR GATESANY TWO SIGNALS MAY BE
COMPLEMENTED
PARITY
COMBINATIONAL LOGIC DESIGN PRACTICESDOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
COMPARATORSEQUALITY - COMPARATORSARITHMETIC RELATIONSHIP -
MAGNITUDE COMPARATORS
4-BIT COMPARATOR
ITERATION?n. THE ACTION OR A PROCESS OF
REPEATING AS: A PROCEDURE IN WHICH REPETITION OF A
SEQUENCE OF OPERATIONS YIELDS A RESULT SUCCESSIVELY CLOSER TO A DESIRED RESULT
THE REPETITION OF A SEQUENCE OF COMPUTER INSTRUCTIONS A SPECIFIED NUMBER OF TIMES OR UNTIL A CONDITION IS MET
ITERATIVE CIRCUITSITERATIVE ALGORITHM:
1. SET C0 TO INITIAL VALUE, SET i TO 02. USE Ci AND PIi TO TO GET POi AND Ci+1
3. INCREMENT i 4. IF i<n GO TO STEP 2
ITERATIVE COMPARATOR
74x85 COMPARATOR
ARITHMETIC CONDITIONS
