Lecture 5Combinational Logic Implementation Using Multiplexers, ROMS, FPGAsPrith BanerjeeECE C03Advanced Digital Logic DesignSpring 1998

ECE C03 Lecture 5

OutlineCombinational Logic ImplementationsMultiplexersDecodersROMSField Programmable Logic ArraysREADING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7

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Use of Multiplexers/SelectorsMulti-point connectionsMUXMUXDEMUXABSumA0A1B0B1SaSbSsS0S1Multiple input sourcesMultiple output destinations

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General Concept of Using Multiplexers2 data inputs, n control inputs, 1 output

used to connect 2 points to a single point

control signal pattern form binary index of input connected to outputnnTwo alternative formsfor a 2:1 Mux Truth TableZ = A' I + A I01Functional formLogical form

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Use of Multiplexers/SelectorsZ = A' I + A I01Z = A' B' I0 + A' B I1 + A B' I2 + A B I3Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7In general, Z = S m I2 -1nk=0kkin minterm shorthand form for a 2 :1 MuxnA Z A B Z A B Z C

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Alternative ImplementationGate LevelImplementationof 4:1 MuxTransmission GateImplementation of4:1 Muxthirty six transistorstwenty transistorsI3I0I2I1ABZ

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Design of Large MultiplexersLarge multiplexers can be implemented by cascaded smaller onesControl signals B and C simultaneouslychoose one of I0-I3 and I4-I7

Control signal A chooses which of theupper or lower MUX's output to gate to Z01S01S01S01S01S123S0CABI0I1I2I3I4I5I6I7CCCZAlternative 8:1 Mux ImplementationS Z A C B 0 1

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Multiplexers/Selectors as General Purpose Blocks2 :1 multiplexer can implement any function of n variables

n-1 control variables; remaining variable is a data input to the muxn-1Example:F(A,B,C) = m0 + m2 + m6 + m7= A' B' C' + A' B C' + A B C' + A B C

= A' B' (C') + A' B (C') + A B' (0) + A B (1)8:1 MUX1 0 1 0 0 0 1 10 1 2 3 4 5 6 7S2 S1 S0ABCF"Lookup Table"S1 S0AB4:1 MUX0 1 2 3CC01FA 0 0 0 0 1 1 1 1B 0 0 1 1 0 0 1 1C 0 1 0 1 0 1 0 1F 1 0 1 0 0 0 1 1CC01

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Generalization of Multiplexer/Selector Logic F 0 1 n-1 Mux control variablessingle Muxdata variableFour possibleconfigurations of the truth table rowsCan be expressed asa function of In, 0, 1Example:G(A,B,C,D) can be implemented by an 8:1 MUX:K-mapChoose A,B,Cas control variablesMultiplexerImplementationTTL package efficientMay be gate inefficientG A B C

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Decoders/DemultiplexersDecoder: single data input, n control inputs, 2 outputs

control inputs (called select S) represent Binary index of output to which the input is connected

data input usually called "enable" (G)n1:2 Decoder:O0 = G S; O1 = G S2:4 Decoder:O0 = G S0 S1

O1 = G S0 S1

O2 = G S0 S1

O3 = G S0 S13:8 Decoder:O0 = G S0 S1 S2

O1 = G S0 S1 S2

O2 = G S0 S1 S2

O3 = G S0 S1 S2

O4 = G S0 S1 S2

O5 = G S0 S1 S2

O6 = G S0 S1 S2

O7 = G S0 S1 S2

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Alternative Implementations1:2 Decoder, Active High Enable1:2 Decoder, Active Low Enable2:4 Decoder, Active High Enable2:4 Decoder, Active Low EnableOutput0GSelectOutput1Output0/GSelectOutput1Select0Select1Output2Output3Output0GOutput1Select0Select1Output2Output3Output0/GOutput1

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Switch Level ImplementationsSelectSelectSelectSelectGOutput0SelectSelectOutput1SelectSelect"0""0"SelectSelectSelectSelectGOutputOutput01Naive, Incorrect Implementation

All outputs not driven at all timesCorrect 1:2 Decoder Implementation

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Switch Implementation of 2:4 DecoderOperation of 2:4 DecoderS0 = 0, S1 = 0

one straight thru path

three diagonal paths

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Decoder as a Logic Building BlockDecoder Generates AppropriateMinterm based on Control SignalsExample Function:F1 = A' B C' D + A' B' C D + A B C DF2 = A B C' D' + A B CF3 = (A' + B' + C' + D')A B C Enb

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Decoder as a Logic Building BlockA Enb B C D If active low enable, then use NAND gates!

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Alternative Implementation of 32:1 MuxMultiplexer OnlyMultiplexer + Decoder10151WY165S2 S1 S0I7F(A, B, C, D, E)I0I15I23I31I6I5I4I3I2I1ABC D EF(A, B, C, D, E)

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5:32 Decoder5:32 Decoder Subsystem\ENS4 S3 S2 S1 S0. . .\Y31\Y0\ENS2 S1 S0S2 S1 S0S2 S1 S0S2 S1 S0\Y31\Y30\Y29\Y28\Y27\Y26\Y25\Y24\Y23\Y22\Y21\Y20\Y19\Y18\Y17\Y16\Y15\Y14\Y13\Y12\Y11\Y10\Y9\Y8\Y7\Y6\Y5\Y4\Y3\Y2\Y1\Y0

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Read-Only MemoriesROM: Two dimensional array of 1's and 0'sRow is called a "word"; index is called an "address"

Width of row is called bit-width or wordsize

Address is input, selected word is outputDec0n-1Address2 -1n0Word Line 0011 Word Line 1010Bit LinesjiInternal Organization

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Implementing Logic with ROMsF0 = A' B' C + A B' C' + A B' C

F1 = A' B' C + A' B C' + A B C

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C'address outputs A B C Address by

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ROMs vs PLAsNot unlike a PLAstructure with afully decodedAND array!ROM vs. PLA:ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions

ROM problem: size doubles for each additional input, can't use don't cares

PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions

PAL problem: constrained fan-ins on OR planesDecoder

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Read-Only Memories2764 EPROM8K x 816K x 16 Subsystem2764A0A1A2A3A4A5A6A7A8A9O0O1O2O3O4O5O6O7OECSPGMVPPA10A11A12A0A1A2A3A4A5A6A7A8A9O0O1O2O3O4O5O6O7OECSPGMVPPA10A11A12D7:D0D15:D8U3U2U1U0

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Combinational Design with FPGAsProgrammable Logic Devices = PLDField Programmable Gate Arrays = FPGAs Altera MAX Family

Actel Programmable Gate Array

Xilinx Logical Cell ArrayPALs, PLAs = 10 - 100 Gate Equivalents100 - 1000(s) of Gate Equivalents!

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Altera Erasable Programmable Logic DevicesClk MUXOutput MUXQF/B MUXInvert ControlAND ARRAYCLKpadHistorical Perspective: PALs same technology as programmed once bipolar PROM EPLDs CMOS erasable programmable ROM (EPROM) erased by UV light

Altera building block = MACROCELL8 Product TermAND-OR Array+ProgrammableMUX'sProgrammable polarityI/O PinSeq. LogicBlockProgrammable feedback

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Altera EPLDsAltera EPLDs contain 8 to 48 independently programmed macrocellsPersonalized by EPROM bits:Flipflop controlledby global clock signal

local signal computesoutput enableFlipflop controlledby locally generatedclock signal+ Seq Logic: could be D, T positive or negative edge triggered+ product term to implement clear functionSynchronous ModeAsynchronous ModeGlobal CLKOE/Local CLKEPROM Cell1Global CLKOE/Local CLKEPROM Cell1Clk MUXClk MUXQQ

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Altera EPLDsLAB ALAB HLAB BLAB GLAB CLAB FLAB DLAB EP I AAND-OR structures are relatively limited Cannot share signals/product terms among macrocellsAltera solution: Multiple Array Matrix (MAX)LogicArrayBlocks

(similar tomacrocells)Global Routing:ProgrammableInterconnectArray8 Fixed Inputs52 I/O Pins8 LABs16 Macrocells/LAB32 Expanders/LABEPM5128:

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Altera EPLDsLAB ArchitectureExpander Terms shared among allmacrocells within the LABMacrocell ARRAYI/O BlockExpander Product Term ARRAYI NPUTSP I AI/O PadI/O PadMacrocell P-TermsExpander P-Terms

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Altera EPLDsP22V10 PAL0ASYNCHRONOUS RESET (TO ALL REGISTERS)23AR8813217622026430835239644222OUTPUT LOGIC MACROCELLP - 5810 R - 5811528572616660704748792836484880440213OUTPUT LOGIC MACROCELLP - 5812 R - 581310561100114411881232127613201364101214089249681452204OUTPUT LOGIC MACROCELLP - 5814 R - 5815167217161760180418481892193619801628202414961584206815402112195OUTPUT LOGIC MACROCELLP - 5816 R - 58172376242024642508255225962640268423322728215622882772224422002816286011001001DQQSP105808PR580910481216202428323640INCREMENTFIRST FUSE NUMBERS159OUTPUT LOGIC MACROCELLP - 5824 R - 582549725016506051045148519252365280492853244884177OUTPUT LOGIC MACROCELLP - 5820 R - 5821382838723916396040044048409241363784418036523740422436964268168OUTPUT LOGIC MACROCELLP - 5822 R - 58234444448845324576462046644708475244004796431243564840186OUTPUT LOGIC MACROCELLP - 5818 R - 5819312431683212325633003344338834323080347629043036352029922948356436081410OUTPUT LOGIC MACROCELLP - 5826 R - 582754125456550055445588563256765720536811576413SYNCHRONOUS PRESET (TO ALL REGISTERS)0481216202428323640INCREMENTSupports large number of product terms per outputLatches and muxes associated with output pins

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Actel Programmable Gate ArraysRows of programmablelogic building blocks

+

rows of interconnectAnti-fuse Technology:Program Once8 input, single output combinational logic blocks

FFs constructed from discrete cross coupled gatesUse Anti-fuses to buildup long wiring runs fromshort segmentsI/O Buffers, Programming and Test LogicLogic ModuleWiring TracksI/O Buffers, Programming and Test LogicI/O Buffers, Programming and Test LogicI/O Buffers, Programming and Test Logic

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Actel Logic ModuleBasic Module is aModified 4:1 MultiplexerExample: Implementation of S-R Latch2:1 MUXD0D1SOA2:1 MUXD2D3SOB2:1 MUXS0YS12:1 MUX"0"R2:1 MUX"1"S2:1 MUXQ"0"

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Actel InterconnectInterconnection FabricLogic ModuleHorizontal TrackVertical TrackAnti-fuse

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Actel Routing ExampleJogs cross an anti-fuse

minimize the # of jobs for speed critical circuits

2 - 3 hops for most interconnectionsLogic ModuleLogic ModuleLogic Module OutputInputInput

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Xilinx Logic Cell ArraysCMOS Static RAM Technology: programmable on the fly!

All personality elements connected into serial shift register

Shift in string of 1's and 0's on power upGeneral Chip Architecture: Logic Blocks (CLBs) IO Blocks (IOBs) Wiring ChannelsIOBIOBIOBIOBCLBCLBCLBCLBIOBIOBIOBIOBWiring Channels

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Xilinx LCA ArchitectureInputs: Tri-state enable bit to output input, output clocks

Outputs: input bit

Internal FFs for input & output paths

Fast/Slow outputs 5 ns vs. 30 ns rise

Pull-up used with unused IOBsDQOUT INVTS INVOUTPUT SOURCESLEW RATEPASSIVE PULLUPMUXRDQRVccPADOutput BufferTTL or CMOS Input BufferGlobal ResetClocksEnable OutputOutDirect InRegistered InProgram Controlled Options

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Xilinx LCA ArchitectureConfigurable Logic Block: CLB2 FFs

Any function of 5 Variables

Global Reset

Clock, Clock Enb

Independent DINCombinational Function GeneratorDRDQCEMuxDRDQCEMuxMuxMuxMuxA B C D EQ1Q2ResetDINClockClock EnableFGXY

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Xilinx CLB Function GeneratorCLB Function GeneratorAny function of 5 variablesTwo Independent Functionsof 4 variables eachFunction of 5 VariablesFGABCDEQ1Q2Function of 4 VariablesFABCDEQ1Q2Function of 4 VariablesGABCDEQ1Q2

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Xilinx CLB Function GeneratorCertain LimitedFunctions of 6 VariablesFunction of 4 VariablesEABCDQ1Q2Function of 4 VariablesABCDQ1Q2FG

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Xilinx Application Examples5-Input Parity GeneratorImplemented with 1 CLB:F = A xor B xor C xor D xor E2-bit Comparator: A B = C D or A B > C DImplemented with 1 CLB:(GT) F = A C + A B D + B C D(EQ) G = A B C D + A B C D + A B C D + A B C D(this is a different parity generator than the one in Chapter 8!)

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Xilinx Application Examplesn-Input Majority CircuitAssert 1 whenever n/2 or greater inputs are 1n-input Parity Functions 5 input = 1 CLB, 2 Levels of CLBs yield up to 25 inputs!CLB5-input Majority CircuitCLBCLBCLB7-input Majority CircuitCLBCLB9 Input Parity Logic

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Xilinx Application Examples4-bit Binary AdderCLBA0B0CinS0CLBA1B1S1CLBA2B2C1S2CLBA3B3C2S3C0CoutS0S1C2A1B1CinA0B0CLBS2S3CoutA3B3A2B2CLBFull Adder, 4 CLB delays tofinal carry out2 x Two-bit Adders (3 CLBseach) yields 2 CLBs to finalcarry out

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Xilinx Interconnect ArchitectureInterconnectDirect Connections

Global Long Line

Horizontal/Vertical Long Lines

Switching Matrix ConnectionsXYCLB3ADDIBCKERCEXYCLB1ADDIBCKERCEXYCLB0ADDIBCKERCEDirect ConnectionsHorizontal Long LineVertical Long LinesGlobal Long LineSwitching MatrixHorizontal Long LineXYCLB2ADDIBCKERCE

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Comparison of Recent Xilinx Architectures

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Parameter

XC 4025

XC3195

XC 2018

Number of FFs

2560

1320

174

Number of I/Os

256

176

74

Number of logic inputs per CLB

9

5

4

Function generators per CLB

3

2

2

Fast Carry Logic

yes

no

no

Number of logic outputs per CLB

4

2

2

RAM bits

32768

0

0

SummaryCombinational Logic ImplementationsMultiplexersDecodersROMSField Programmable Logic ArraysREADING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7

ECE C03 Lecture 5