DIGITAL SYSTEMS TCE1111 1 OTHER COMBINATIONAL LOGIC CIRCUITS DECODERS.
ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Decoders.
17
ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Decoders
-
Upload
melinda-mcbride -
Category
Documents
-
view
243 -
download
1
Transcript of ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Decoders.
ECE 2110: Introduction to Digital Systems
Chapter 6 Combinational Logic Design Practices
Decoders
2
Previous…
• Circuit Timing
3
Decoder
Multiple-input/multiple-output device. Inputs ( n ) are less than outputs ( m ). Converts input code words into output
code words. One-to-One mapping :
- Each input code produces only one output code.
Input codes :- Binary Code- Your Code !
Output Codes1-out-of-m code Gray Code BCD Code
enable inputs
4
Display Decoders
Seven segment display for decimal digits.Consider the function for the ‘a’ (top
segment) signal.How many inputs?Design the decoder:
SOP vs. POS
5
Binary Decoders
n-to- 2n decoder : n inputs and 2n outputs. Input code : n bit Binary Code. Output code : 1-out-of- 2n , One output is asserted for each input
code. Example : n=2, 2-to-4 decoder
Note “x” (don’t care input notation).
6
Binary 2-to-4 decoder
7
MSI Binary 2-to-4 decoder: 74x139
Input buffering (less load)NAND gates (faster)
8
74x139 : Logic Symbol -Truth Table
G Y0
Y1
Y2
Y3
A
B
• Active Low Enable, Active Low outputs
• Truth Table Logic Symbol
Inputs OutputsG_L B A Y3-L Y2-L Y1-L Y0_L 1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1
G_L
A
B
Y0_L
Y1_L
Y2_L
Y3_L
1/2 74x139
9
Complete 74x139 Decoder
10
74x138: 3-to-8 Binary decoder
11
74x138: Logic Symbol
12
74x138: Truth Table
13
Decoders as logic function generators
Advantages : - Flexibility- Multiple-output Logic functions
Disadvantages :- Complexity : for large number of inputs ( 5-variable Function with 3 minterms ! F= AB’CD’E + A’BC’DE+A’BCDE’ )
14
Implementing the Canonical Sum
The binary decoder generates all minterms of n-variable logic function.
The canonical sum ( sum of minterms ) of a logic functions is obtained by adding all minterms of that function:
-Match the order of input bits-Activate Enable inputs
Example :
G2A
Y0
Y1
Y2
Y3
A
B
Z
Y
74x138
Y4
Y5
Y6
Y7CX
G2B
G1
FX Y Z
( , , ), ,
2 4 7F
+5V
15
Decoder cascading
4-to-16 decoder
16
Decoder applications
Microprocessor memory systemsselecting different banks of memory
Microprocessor input/output systemsselecting different devices
Microprocessor instruction decodingenabling different functional units
Memory chipsenabling different rows of memory depending on
addressLots of other applications
17
Next…
Encoders
Reading Wakerly CH-6.5
