Lab 3: Decoders, Mux, ROM and PAL• Implement combinational circuits using

– decoders

– multiplexers

– ROMs

– PALs

• OrCAD– schematic entry and simulation

• Programmer– program logic devices

Decoders• A n-to-m decoder

– a binary code of n bits = 2n distinct information

– n input variables; up to 2n output lines

– An example

– only one output can be active (high) at any time

• Combinational logic implementation– each output = a minterm

– use a decoder and an external OR gate = sum of minterm

– implement any Boolean function of n input variables

• 74154: 4x16 decoder– propagation delay: 23 ns

– or 18 ns from strobes

• Example 5-1– A full-adder

– S(x,y,x)=(1,2,4,7)

– C(x,y,z)= (3,5,6,7)

– two possible approaches using decoder• OR(minterns of F): k inputs

• NOR(minterms of F'): 2n - k inputs

– In general, it is not a practical implementation

• Gate-level and pin-outs 74154 +------\/------+ 1 -|/0 Vcc|- 24 2 -|/1 a0|- 23 3 -|/2 a1|- 22 4 -|/3 a2|- 21 5 -|/4 a3|- 20 6 -|/5 /cs1|- 19 7 -|/6 /cs0|- 18 8 -|/7 /15|- 17 9 -|/8 /14|- 1610 -|/9 /13|- 1511 -|/10 /12|- 1412 -|gnd /11|- 13 +--------------+

Multiplexers• A digital multiplexer

– select binary information from one of many input lines and direct it to a single output line

– 2n input lines, n selection lines and one output line

– e.g.: 4-to-1 multiplexer

– a decoder + OR

• 74151– 3-to-8 decoder

– an enable input

• 2n-to-1 MUX

– implement any Boolean function of n+1 input variables• n of these variables: the selection lines

• the remaining variable: the inputs

– an example: F(A,B,C)=(1,3,5,6)

• Procedure:– assign an ordering sequence of the input variable

– the leftmost variable (A) will be used for the input lines

– assign the remaining n-1 variables to the selection lines w.r.t. their corresponding sequence

– list all the minterms in two rows (A' and A)

– circle all the minterms of the function

– determine the input lines

• An example: F(A,B,C,D)=(0,1,3,4,8,9,15)

PLD (Programmable Logic Devices)• A structural design approach

• FPGA (Field Programmable Gate Array)– large capacity( > 10K gates)

– (re)programmable logic block and interconnections

– rapid prototyping

– E.g., Xilinx FPGA

ROM• ROM

– a memory device of permanent binary information

– n input lines: address

– m output lines: word (data)

– 2n distinct address = 2

n distinct

words

• Another viewpoint

– a decoder that generates the 2n

minterms

– plus m OR gates

– can be used to implement any Boolean functions of n input variables

– a fixed AND array and a programmable OR array

n inputs m outputs2

n x m

ROM

• A 32x4 ROM – applications• permanent storage of

program/data

• display character fonts

• a table-look-up log functions?

• combination logic implementations

• code conversion

• combination logic implementation– store the truth table in a ROM

• Types of ROMs– mask programming ROM

• IC manufacturers

• is economical only if large quantities

– PROM: Programmable ROM• fuses

• universal programmer

– EPROM: erasable PROM• floating gate

• ultraviolet light erasable

– EEPROM: electrically erasable PROM• longer time is needed to write

• flash ROM

• limited times of write operations

• 2764– 8k * 8 EPROM

+------\/------+ 1 -|Vpp Vcc|- 28 2 -|A12 /pgm|- 27 3 -|A7 nc|- 26 4 -|A6 A8|- 25 5 -|A5 A9|- 24 6 -|A4 A11|- 23 7 -|A3 /OE|- 22 8 -|A2 A10|- 21 9 -|A1 /CE|- 2010 -|A0 D7|- 1911 -|D0 D6|- 1812 -|D1 D5|- 1713 -|D2 D4|- 1614 -|gnd D3|- 15 +--------------+

2764

A0A1A2A3A4A5A6A7A8A9

O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

A0A1A2A3A4A5A6A7A8A9

O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

• 16K * 16 configuration

++2764

A0A1A2A3A4A5A6A7A8A9

O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

2764

A0A1A2A3A4A5A6A7A8A9

O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

2764

A0A1A2A3A4A5A6A7A8A9

O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

2764

A0A1A2A3A4A5A6A7A8A9

O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

+ +

A13/OE

A12:A0

D7:D0D15:D8

U3 U2

U1 U0

PLA• PLA

– only the needed product terms are generated

– both the AND array and the OR array are programmable

– n inputs, k product terms and m outputs

– the number of fuses: 2n*k+k*m+m

– area(cost) = (n+m)*k

– a regular structure design

• An example PLA

• Types of PLA– mask-programmable

– field-programmable logic array

PAL• PAL

– a programmable AND array and a fixed OR array

– can replace 3-10 TTL IC's

– is not as flexible as the PLA

– can generate any product term

– each OR has only three inputs

• Commercial PAL– more than 8 inputs

– some of the output terminals are sometimes bidirectional

– each OR gate may have 8 inputs

– the fuse pattern may be unreadable

– output terminals may be latched

• 16V8

– 20-pin

– V8• simple I/O

• complex mode

• registered mode

• 16V8

Combinational Logic Word ProblemsBCD to 7 Segment Display Controller

C0 = A + B D + C + B' D'C1 = A + C' D' + C D + B'C2 = A + B + C' + D

C3 = B' D' + C D' + B C' D + B' CC4 = B' D' + C DC5 = A + C' D' + B D' + B C'C6 = A + C D' + B C' + B' C14 Unique Product Terms

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 0 X 1

0 1 X 1

1 1 X X

1 1 X X

K-map for C 0

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 X 1

1 0 X 1

1 1 X X

1 0 X X

K-map for C 1

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 X 1

1 1 X 1

1 1 X X

0 1 X X

K-map for C 2

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 0 X 1

0 1 X 0

1 0 X X

1 1 X X

K-map for C 3

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 0 X 1

0 0 X 0

0 0 X X

1 1 X X

K-map for C 4

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 X 1

0 1 X 1

0 0 X X

0 1 X X

K-map for C 5

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 1

0 1 X 1

1 0 X X

1 1 X X

K-map for C 6

BCD to 7 Segment Display Controller 0

32 64 96

128 160 192 224

First fuse numbers

1

19

2

0 4 8 12 16 20 24 28

256 288 320 352 384 416 448 480

18

3

512 544 576 608 640 672 704 736

17

4

768 800 832 864 896 928 960 992

16

5

1024 1056 1088 1120 1152 1184 1216 1248

15

6

1280 1312 1344 1376 1408 1440 1472 1504

14

7

1536 1568 1600 1632 1664 1696 1728 1760

13

8

1792 1824 1856 1888 1920 1952 1984 2016

12

9 11

Increment

Note: Fuse number = first fuse number + increment

16H8PALCan Implementthe function

BCD to 7 Segment Display Controller

14H8PALCannot Implementthe function

1

2 23

First fuse numbers

0 28 56 84

3

4

14

13

5

6

7

8

9

10

11

21 112 140

20 168 196

19 224 252

18 280 308

17 336 364

16 392 420

1 22

448 476 504 532

15

0 1 2 3 4 8 10 12 14 16 18 20 24 27

Note: Fuse number = first fuse number + increment

Increment

.BEQ Format

– pinlist starts from pin 1

– unused pins (I/O): “nc” or “NC” (a reserved label)

Line Data1 (non-blank) Device name ; comment

2 (non-blank) 1st half of pinlist

3 (non-blank) 2nd half of pinlist

subsequent boolean equations

• Boolean equationoperator function

= assignment to a combinational output

* AND

+ OR

:= assignment to a registered (clocked) output

:+: XOR

/ complement

; comment field delimiter

• An example– MW = /S0 + PW*/DE ; an example

An .BEQ ExamplePAL12H6; an exampleS0 PW DE DA S0 S1 P9 EA E1 GNDE0 EN O3 SS MW LA HA N0 NC VCCMW = /S0 + PW*DELA = /SA * /D0SS = S1*P0*/SAHA = S1*P0*/SA*EA*E1O3 = P0*E0*EAN0 - P0*/EN

Background• Logic Breadboard

• 一字起子 or U-shaped clip

• IC pin numbering: 7400 (four 2-input NAND) +---\/---+ 1 -|1A Vcc|- 14 2 -|1B 4A|- 13 3 -|1/Y 4B|- 12 4 -|2A 4/Y|- 11 5 -|2B 3A|- 10 6 -|2/Y 3B|- 9 7 -|gnd 3/Y|- 8 +--------+

• DIP: Dual In-line Package

• All ICs should be inserted with the same orientation to facilitate wiring and debugging

Wiring• Run all wires around ICs, not over them

– Easy debug and easy replace.

• Try not to cover up too many unused holes with your wires

• Keep wires close to the surface of the breadboard, and make them as short as possible subject to the preceding constraints.

• RED: +5 volts; BLACK: Ground; YELLOW: +12 volts; WHITE: Negative voltage; VIOLET: Control; ORANGE: Data bus; BROWN: Address bus

Wiring Procedure• Wire the power.

• Wire unused inputs: +5V through a 1K current-limiting resistor or ground.

• Wire all regular buses.

• Wire all control lines.

• Check wiring of each IC sequentially.

• Double-check all power connections before applying power

Damage• The one sure way to permanently damage an IC is to

reverse power and ground.

• Most of the time you will NOT damage an IC by shorting one of its outputs.

• The totem-pole outputs can be shorted together or to ground without damage.

• However, when an output trying to maintain a LOW level is shorted to the 5V supply there is usually damage.

Debugging• A small circuit will sometimes work properly the first time

it is turned on

• All other circuits require DEBUGGING

• Use an ohmmeter to perform a continuity check.

• After checking for SMOKE when the circuit is first powered, it is necessary to start debugging at a lower level

• Two types of errors: wiring errors and design errors.

• To work backwards in the circuit from some point that has a predictable behavior

Errors• The most common wiring errors are omitted and misplaced

wires.

• The most common design errors involve the disposition of unused inputs.

• The next most common design errors involve the 1s and 0s catching behavior of master/slave J-K flip-flops.

Operating Characteristics• VCC: Supply voltage

– (4.75V, 5V, 5.25V)

• VIH: high level input voltage– > 2V

• VIL: low level input voltage– < 0.8V

• VOH: high level output voltage– (2.5V, 3.4V, )

• VOL: low level output voltage– ( , 0.35V, 0.5V)

Operating Characteristics• IOH: high level output current

– > -400 uA

• IOL: low level output current– < 8 mA

• IIH: high level input current– < 20 uA

• IIL: low level input current– > -0.4 mA

• ICC: supply current– ( , 6mA, 10 mA)

Propagation Delay• tpd: propagation delay

• tPLH: low-to-high-level output

• tPHL: high-to-low-level output

• tPHZ: disable time from high level

• tPLZ: disable time from low level

• tPZH: enable time from high level

• tPZL: enable time from low level

Intel Hex Format

: start of record

##record length (two ASCII hexdecimal value)

aaaa load address(four ASCII hexdecimal value)

tt record type (two ASCII hexdecimal value)

00: data record

01: end of file record

dd...dd two ASCII hexdecimal value per byte

cc checksum

RecordMark

RecordLength

LoadAddress

RecordType

ProgramData

Check-sum

: ## aaaa tt dd…dd cc

• An example:##aaaattdd............................ddcc:100200002e736e64000000230000198100000002bc:1002100000001f40000000017375626a6563742e60:100220017761768080808081808080808080808000