Chapter 8 Sequential Circuit Design:...

Chapter 8

Sequential Circuit Design:

Principle

ECOM 4311

Digital System Design using VHDL

2

Outline

1. Overview on sequential circuits

2. Synchronous circuits

3. Danger of synthesizing asynchronous circuit

4. Inference of basic memory elements

5. Simple design examples

6. Timing analysis

7. Alternative one-segment coding style

8. Use of variable for sequential circuit

3

Overview on sequential circuit

Combinational vs sequential circuit

• Sequential circuit: output is a function of

current input and state (memory)

Basic memory elements

• D latch

• D FF (Flip-Flop)

• RAM

Synchronous vs asynchronous circuit

4


5


6

• Timing of a D FF:

D Flip Flop

Clock-to-q delay (Tcq): Delay required for sampled d value to show up on q

Setup time (Tsetup): time interval that d must be stable for before the rising edge

of clock

Hole time (Thold): time interval that d must be stable for after the rising edge.

7

Synch vs asynch circuits

Globally synchronous circuit: all memory

elements (D FFs) controlled (synchronized) by

a common global clock signal

Globally asynchronous but locally synchronous

circuit (GALS): Used in cases in which the

components of the design are spread too far

apart to allow a single synchronous clock.

Globally asynchronous circuit

• Use D FF but not a global clock

• Use no clock signal

8

2. Synchronous circuit

Basic Block diagram:

State registers (state_reg) represent the memory

elements

Next state logic represent the combinational circuit that

determines state_next

Output logic represent the combinational circuit that

generates the external output signal.

10

• Operation o At the rising edge of the clock, state_next sampled

and stored into the register (and becomes the new value of state_reg

o The next-state logic determines the new value (new state_next) and the output logic generates the output

o At the rising edge of the clock, the new value of state_next sampled and stored into the register

• Note that the clock period needs to be large enough to

accommodate the propagation delay of the next-state logic, the clock-to-q delay and the setup time of the FFs

Synchronous circuit

11

Advantages of synchronous design

A single global clock makes the task of

satisfying the timing constraints of a design

with of thousands of FFs manageable.

The synchronous model separates the

combinational components from the memory

elements, making it possible to treat the

combinational part by itself

Propagation delay anomalies such as

hazards can be dealt with easily by focusing

on the worst case timing behavior

12

Types of synchronous circuits

Regular sequential circuit

• State representation, transitions and next-state logic

have a simple, regular pattern, as in an incrementor or

shift register.

Random sequential circuit (FSM)

• More complicated state and no special relationship

between st ates transitions and their binary

representations -- next-state logic is random

Combined sequential circuit (FSM with a Data

path, FSMD -- RTL)

• Combines regular sequential circuit and an FSM, with

FSM acting as control for the sequential circuit

13

Danger of synthesizing asynchronous

circuit

Consider the D Latch described earlier

We can write VHDL code as follows to represent

it

14

Danger of synthesizing asynchronous

circuit

•Here we see the

implementation is

combinational except for

that the output is looped

around as an input

•Unfortunately, there is a

serious timing problem with

this circuit

15

Inference of basic memory elements

VHDL code should be clear so that the pre-

designed cells can be inferred

VHDL code

• D Latch

• Positive edge-triggered D FF

• Negative edge-triggered D FF

• D FF with asynchronous reset

16

D Latch

• No else branch

• D latch will be

inferred

17

Pos edge-triggered D FF

18

Neg edge-triggered D FF

19

D FF with async reset

20

Register

•Multiple D FFs

with same clock

and reset

21

5. Simple design examples

• Follow the block diagram

oRegister

oNext-state logic (combinational circuit)

oOutput logic (combinational circuit)

22

D FF with sync enable

• Note that the en is controlled by clock

23

D FF with sync enable Conceptual diagram

24

T FF

25

T FF

26

Free-running shift right register

27


28


29

Universal shift register

• 4 ops: parallel load, shift right, shift left, pause

30


31


32

Arbitrary sequence counter

33

Arbitrary sequence counter

34

Free-running binary counter • Count in binary sequence

• With a max_pulse output: asserted when

counter is in “11…11” state

35

Free-running binary counter

36

• Wrapped around automatically

• Poor practice:

Free-running binary counter

37

Featured Binary counter

38


39


40

Decade (mod-10) counter

41

Decade (mod-10) counter

42

Programmable mod-m counter

43

Programmable mod-m counter

45

Programmable mod-m counter more efficient

implementation

46

6. Timing analysis

Combinational circuit:

• characterized by propagation delay

Sequential circuit:

• Has to satisfy setup/hold time constraint

• Characterized by maximal clock rate

(e.g., 200 MHz counter, 2.4 GHz Pentium II)

• Setup time and clock-to-q delay of register and

the propagation delay of next-state logic are

embedded in clock rate

47

• Setup time violation and maximal clock rate

49

• E.g., shift register; let Tcq=1.0ns Tsetup=0.5ns

50

• E.g., Binary counter; let Tcq=1.0ns Tsetup=0.5ns

52

• Hold time violation

54

Using Variables in Sequential

Circuit Descriptions

A variable can also be assigned under the

clk’event and clk = ’1’ condition, but

whether a FF is created or not depends on

how it is used

If a variable is assigned a value before it is

used, it will get a value on each invocation

of the process and therefore, there is not

need to remember its previous value

Chapter 8 Sequential Circuit Design:...

Documents

Transcript of Chapter 8 Sequential Circuit Design:...