IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 5, MAY 2012 269

A 0.2–2.6 GHz Wideband Noise-ReductionGm-Boosted LNA

Hua-Chin Lee, Member, IEEE, Chao-Shiun Wang, Member, IEEE, and Chorng-Kuang Wang, Fellow, IEEE

Abstract—This letter presents a wideband low-noise amplifier(LNA) which utilizes ��-boosted and noise-reduction techniques.The proposed DC-coupled 2-stage LNA employs an error am-plifier to cancel the DC-offset voltage between the differentialDC-coupled paths. The LNA is implemented in 90-nm digitalCMOS technology. Within 0.2–2.6 GHz wideband applications,the LNA achieves 24 dB voltage gain, 1.9–2.9 dB NF, 3 dBmIIP3. The core power of the LNA draws 9 mA from 1 V supplyvoltage and occupies 0.046 ���.

Index Terms—DC-offset cancellation, ��-boosted, low-noiseamplifier (LNA), noise-reduction.

I. INTRODUCTION

R ECENTLY, cognitive radio (CR) and software-definedradio (SDR) receivers have been considered as future

wireless systems to alleviate bandwidth and channel conges-tion. However, such kind of agile systems need to operate withwideband frequency channels, and one of the key circuit blocksin the analog front-end of the receiver chain demands a wide-band LNA or several narrowband LNAs [1]. Thus, the LNAshould meet some rigorous requirements such as widebandinput matching, low noise figure and sufficient gain within thewideband range [2].

In this letter, the design of the proposed LNA will focus onwideband input matching, gain boosting and low noise figuretechniques. Therefore, a single wideband LNA which covers allthe frequency bands is preferred by considering the power andcircuit complexity issues. In order to provide sufficient gain ofthe LNA, the -boosted technique is also used in the same gainstage. By using the capacitive feedback loop in the gain stage,the noise reduction can then be achieved at the same time.

II. PROPOSED LNA CIRCUIT TOPOLOGY

In order to achieve high gain without dissipating too muchpower, -boosted topology is a good candidate to provide thisrequirement [3]–[5]. To reduce the even-order harmonics of thereceiver, the LNA is needed to act as a single-to-differential con-version as well.

The common-gate LNA (CGLNA) architecture has broad-band input matching, linearity and stability [3]–[9]. The noise

Manuscript received February 11, 2012; accepted February 23, 2012. Date ofpublication April 16, 2012; date of current version May 04, 2012. This work wassupported by NTU-MediaTek Wireless Research Lab (founded by MediaTekInc.) and TSMC University Shuttle Program.

The authors are with the Graduate Institute of Electronics Engineering, Col-lege of Electrical Engineering and Computer Science, National Taiwan Univer-sity, Taipei 106, Taiwan (e-mail: huachin@aic.ee.ntu.edu.tw; cswang@aic.ee.ntu.edu.tw; ckwang@cc.ee.ntu.edu.tw).

Color versions of one or more of the figures in this letter are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LMWC.2012.2191275

Fig. 1. Proposed noise-reduction � -boosted LNA.

factor of conventional CGLNA is limited to with thecondition of , where and are empirical process-and bias-dependent parameters, respectively [5]–[8]. Hence, theproposed -boosted technique boosts the effective to

, and the noise factor can be reduced to, where is the equivalent inverting gain between gate

and source of input MOS device.Fig. 1 shows the proposed noise-reduction -boosted

LNA with internal DC-offset cancellation. The proposed LNAis a common-gate amplifier topology with the -boostedtechnique and demonstrates wideband, low power and high dy-namic range. This topology avoids using an external widebandbalun which possesses inevitable losses. The wideband inputmatching consists of the C-G amplifier M1 with the -boostedapproach. The inverting gain for -boosted is realized by aC-S amplifier M2n. The parallel transistor M2p is used toreduce the current flowing from resistor R2 and increase theC-S amplifier gain as well. A differential pair amplifier is con-nected to reduce the common noise and even-order harmonicsdistortion. To alleviate the output dc offset, an error amplifier isemployed to feedback control the PMOS transistor Mfb.

The on-chip error amplifier acts as a differential-to-single am-plifier with capacitive output loading. The output node with ex-ternal capacitor acts as a low pass filter and performs the corre-sponding dc voltage with the differential inputs.

Therefore, the input impedance [3], [4] is deduced as

(1)

The first stage is constructed from the C-G (M1) and C-S(M2n//M2p, M3) stages in parallel. The first stage small signalgain of the C-G and the C-S can be derived as follows:

(2)

(3)

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270 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 5, MAY 2012

Fig. 2. Die micrograph of the proposed LNA.

Fig. 3. S-parameter measurement results.

where R1 is the load resistor of the C-G amplifier and R2 is theload resistor of the C-S amplifier.

The output gain of the C-G amplifier is the ratio between theinput source resistor and the output load resistor. In order to gen-erate differential signal in the first stage, the small signal gain atoutputs and should be set to equal. According to(2) & (3), the differential gain of the first-stage amplifier equals

which isindependent to the impedance matching of the amplifier.

The equivalent noise current transfer function from the inputmatching transistors M1 and M2 can be derived as

(4)

(5)

where .Using this topology and (4), the transfer function of the equiv-

alent noise current source between the drain and the source ofthe input matching transistor M1 to the differential output is can-celled under the condition of . The differentialoutput property results in the noise from M1 to be neutralized.

Fig. 4. Measurement and post-layout simulation for noise figure.

Fig. 5. IIP2 and IIP3 measurement and post-layout simulation results(differential).

However, the noise of C-S transistor remains according to thederivation of (5). In order to reduce the noise contribution of theC-S transistor M2, the should be carefully chosen.

Equation (6) shows the total noise factor of the proposed2-stage LNA

(6)

where is the output noise due to M2n and M2p. In (6),the output noise due to M1 is cancelled according to the cancel-lation of the same noise contribution at node and .The output noise due to M3 is zeroed with regard to the highoutput impedance of M2 and the output noise due to Ms is alsozeroed with the source-coupled pair topology. According to thistopology, the differential post-layout simulation of noise figure

LEE et al.: 0.2–2.6 GHZ WIDEBAND NOISE-REDUCTION GM-BOOSTED LNA 271

Fig. 6. Gain and phase error.

TABLE IPERFORMANCE COMPARISONS

including pads

is 1 dB lower than the single output noise figure which is shownin Fig. 4.

Furthermore, if the phase error exists in differential outputsof the single-to-differential stage, respectively, the outputs of theoutput stage remains differential

The differential outputs of the output stage

(7)

From (7), the 90 phase error only causes 3 dB output lossin magnitude and the output still maintains differential. If thecommon-mode signal cannot be equaled at outputs ofand , the followed source-coupled pair will amplify thedc offset. Hence, the error amplifier is needed to implement onchip to solve this problem.

III. EXPERIMENTAL RESULTS

Fig. 2 shows the chip micrograph of the proposed LNA. Thecore circuit occupies 0.046 excluding pads and consumes8 mW from a 1 V supply voltage. On-wafer measurements weremade on the noise-reduction -boosted LNA chip.

Fig. 3 and Fig. 4 demonstrate the experimental results ofS-parameter and noise figure from the LNA chip. The LNA wasmeasured on the open-source buffer outputs with the externalbias-T and balun, and the measured gain and differential noisefigure are 24 dB and 1.9–2.9 dB, respectively. From (6), the the-oretical noise figure is 2.1 (single) which gives a 1st-order de-sign parameter for the proposed LNA. The IIP3 was measured

from 200 MHz to 3 GHz using 8 MHz tone spacing. Fig. 5 de-picts that the measured IIP2 and IIP3 are 22.5 dB and 3 dB,respectively. Fig. 6 shows the gain error and phase error are av-eraged at 0.2 dB and 2 degree, respectively. Comparison withother LNA’s is summarized in Table I [10], [11] where figure ofmerit (FOM) is defined as follows [12]:

(8)

IV. CONCLUSION

A wideband noise-reduction -boosted LNA for widebandradio applications has been proposed and demonstrated in a90-nm digital CMOS technology. First of all, the proposedcapacitive-coupling -boosted LNA provides wideband inputmatching. The noise-reduction architecture provides low noisefigure around 2.9 dB with bandwidth of 2.6 GHz. The internalerror amplifier cancels the internal dc-offset voltage betweentwo stages and does not increase too much loading. The LNAhas then been fabricated and a complete measurement has beenaccomplished to prove the performance of the proposed ar-chitecture. The experimental results confirm that the proposedLNA presents great potential for future wireless communica-tion systems such as TV-band cognitive radio, a 4 G wirelessstandard or SDR over ISM bands.

ACKNOWLEDGMENT

The authors would like to thank Dr. S.-Y. Ho, K.-Y. Wang,T.-T. Lu H.-H. Chiang, and M.-Y. Hsu for valuable comments.

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