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    Thoai Nam

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Flynns Taxonomy

    Classification of Parallel Computers Basedon Architectures

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Based on notions of instruction and data streams SISD (S ingle Instruction stream, a S ingle Data stream ) SIMD (S ingle Instruction stream, Multiple Data streams ) MISD (Multiple Instruction streams, a S ingle Data stream)

    MIMD (Multiple Instruction streams, Multiple Data stream)Popularity MIMD > SIMD > MISD

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    SISD Conventional sequential machines

    IS : Instruction Stream DS : Data StreamCU : Control Unit PU : Processing UnitMU : Memory Unit

    CU PU MU

    IS

    IS DSI/O

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    SIMD Vector computers, processor arrays Special purpose computations

    PE : Processing Element LM : Local Memory

    CU

    PE 1 LM 1

    PE n LM n

    DS

    DS

    DS

    DS

    ISIS

    Program loadedfrom host

    Data sets

    loaded from host

    SIMD architecture with distributed memory

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    MISD Systolic arrays Special purpose computations

    Memory(Program,

    Data)PU 1 PU 2 PU n

    CU 1 CU 2 CU n

    DS DS DSIS IS

    IS IS

    IS

    DSI/O

    MISD architecture (the systolic array)

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    MIMD

    General purpose parallel computers

    CU 1 PU 1

    SharedMemory

    IS

    IS DS

    I/O

    CU n PU nIS DSI/O

    IS

    MIMD architecture with shared memory

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Classification based on

    Architecture

    Pipelined Computers

    Dataflow ArchitecturesData Parallel SystemsMultiprocessorsMulticomputers

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Instructions are divided into a number of steps

    (segments, stages) At the same time, several instructions can beloaded in the machine and be executed in

    different steps

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    IF instruction fetch ID instruction decode and register fetch

    EX- execution and effective address calculation MEM memory access WB- write back

    Instruction i IF ID EX WB

    IF ID EX WB

    IF ID EX WB

    IF ID EX WB

    IF ID EX WB

    Instruction i+1

    Instruction i+2

    Instruction i+3

    Instruction # 1 2 3 4 5 6 7 8

    Cycles

    MEM

    MEM

    MEM

    MEM

    MEM

    9

    Instruction i+4

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Data-driven model

    A program is represented as a directed acyclic graph inwhich a node represents an instruction and an edgerepresents the data dependency relationship between theconnected nodes

    Firing rule A node can be scheduled for execution if and only if its

    input data become valid for consumption

    Dataflow languages Id, SISAL, Silage, LISP,... Single assignment, applicative(functional) language

    Explicit parallelism

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    z = (a + b) * c+

    *

    a

    b

    c

    z

    The dataflow representation of an arithmetic expression

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Execution of instructions is driven by data availability

    What is the difference between this and normal (controlflow) computers?

    Advantages Very high potential for parallelism High throughput Free from side-effect

    Disadvantages Time lost waiting for unneeded arguments High control overhead Difficult in manipulating data structures

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    input d,e,f

    c0 = 0

    for i from 1 to 4do

    beginai := d i / e i

    b i := a i * f ici := b i + c i-1

    end

    output a, b, c

    /

    d1 e1

    *

    +

    f 1

    /

    d2 e2

    *

    +

    f 2

    /

    d3 e3

    *

    +

    f 3

    /

    d4 e4

    *

    +

    f 4

    a1

    b1

    a2

    b2

    a3

    b3

    a4

    b4

    c0 c4c1 c2 c3

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Execution on

    a Control Flow Machine

    a1 b1 c1 a2 b2 c2 a4 b4 c4

    Sequential execution on a uniprocessor in 24 cycles

    Assume all the external inputs are available before entering do loop+ : 1 cycle, * : 2 cycles, / : 3 cycles,

    How long will it take to execute this program on a dataflowcomputer with 4 processors?

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Execution on

    a Dataflow Machine

    c1 c2 c3 c4a1

    a2

    a3

    a4

    b1

    b2

    b4

    b3

    Data-driven execution on a 4-processor dataflow computer in 9 cycles

    Can we further reduce the execution time of this program ?

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Programming model

    Operations performed in parallel on each elementof data structure

    Logically single thread of control, performs

    sequential or parallel steps Conceptually, a processor associated with each

    data element

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    SIMD Architectural model Array of many simple, cheap processors with little

    memory each Processors dont sequence through instructions

    Attached to a control processor that issuesinstructions

    Specialized and general communication, cheap globalsynchronization

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Instruction set includes operations on vectors

    as well as scalars2 types of vector computers Processor arrays Pipelined vector processors

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    A sequential computer connected with a set of identical processingelements simultaneouls doing the same operation on different data.

    Eg CM-200

    Data path

    Processingelement Data

    memory

    I n t e r c o n n e c

    t i o n n e

    t w o r k

    Processingelement Data

    memory

    Processingelement Data

    memory

    I/0

    Processor array

    Instruction path

    Program and

    Data Memory

    CPU

    I/O processor

    Front-end computer

    I/0

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Stream vector from

    memory to the CPUUse pipelinedarithmetic units to

    manipulate dataEg: Cray-1, Cyber-205

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Consists of many fully programmable

    processors each capable of executing its ownprogramShared address space architectureClassified into 2 types Uniform Memory Access (UMA) Multiprocessors

    Non-Uniform Memory Access (NUMA)Multiprocessors

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Uses a central switching mechanism to reach a centralizedshared memory

    All processors have equal access time to global memoryTightly coupled systemProblem: cache consistency

    P1

    Switching mechanism

    I/O

    P2 Pn

    Memory banks

    C1 C2 Cn Pi

    Ci

    Processor i

    Cache i

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Shared-bus switching mechanism

    Mem Mem Mem Mem

    CacheP

    I/OCacheP

    I/O

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Packet-switched network

    Network

    Mem Mem

    Cache

    P

    Cache

    P

    Cache

    P

    Mem

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa Tp.HCM

    Distributed shared

    memory combinedby local memory ofall processorsMemory accesstime depends onwhether it is localto the processor

    Caching shared(particularlynonlocal) data?

    Network

    Cache

    P

    Mem Cache

    P

    Mem

    Cache

    P

    Mem Cache

    P

    Mem

    Distributed Memory

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    Khoa Cong Nghe Thong Tin ai Hoc Bach Khoa