Post on 21-Jan-2016
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
4. Introducing 90nm technology
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
• Towards nano-scale• Mos devices • Specific features• • conclusion
Summary
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
1. Towards nano-scale
• ST, Motorola and philips at Crolles, France
• 90nm core process• Specific features for each
partner
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
83 86 89 92 95 98 01 04
0.1
80286 80386486
pentium
pentium II
1.0
0.2
0.3
2.0
0.05
Year
Pentium IV
0.03
Itanium
07
Micron Sub-micron Deep-submicron
UltraDeep-sub
micron
Nano
1. Towards nano-scale
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
1. Towards nano-scale
Already 90nm?130nm to 90nm• improvement in logic density• power saving per gate• reduction in gate delay
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
• Shallow Trench Isolation• Triple Well• Dual Vt• Triple Oxide Option• Dual Poly Gate • Cu Metalup to 9 Layers with Low-k • Metal pitch 0.3µm (m1-6), 0.6µm (m7-8), 1.2µm (m9)• Wire Bond / Flip Chip• Same Process for Logic & Mixed Mode (for SOC Application)• Various power supplies supported: 3.3V, 2.5V, 1.8V, 1.2V, 1V
1. Towards nano-scale
General CMOS 90nm Specifications
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
1. Towards nano-scale
UMC CMOS 90nm
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
1. Towards nano-scale
300mm wafers In a 300mm fab…
UMC taiwan
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
2. Mos devices
UMC CMOS 90nm Specifications (www.umc.com)
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
2. Devices
© Fujitsu
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
SP_Lvt
2. Mos devices
SP SP_HvtIO_2.5 IO_2.3
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
2. Mos devices
• Low Vt
• High speed (Or SP)
• Low leakage (Or HVt)
• High voltage: for I/Os
• Double-gate:
• Ultra-low leakage (Or LL)
• Output pad
• Input pad
Critical path
Standard Core
Low power
EEPROM, Flash
Ultra low power
High voltage
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
3. Specific features
Triple wellShallow Trench Isolation
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
3. Specific features
Triple wellShallow Trench Isolation
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
Cmos Embedded memories
Volatile
eDRAM SRAM
Non volatile
ROM EEPROM FRAM
• 80% of a system-on-chip• Bottleneck for bandwidth
4. Embedded Memory
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
4. Embedded Memory
Embedded DRAM (e-dram)
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
4. Embedded Memory
Embedded DRAM (ST style)
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
The next major evolution?
Less capacitance
Less distance between nMOS and pMOS
Less leakage
CMOS compatible
>50% faster circuits
Kink effectFully or partially depleted?
5. Silicon-On-insulator
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
Towards 2000 pins
6. Packaging
E. Sicard - introducting 90nm
Master in Microelectronics technology and Manufacturing Management
6. Conclusion
• The ultra-deep submicron technologies introduce new features
• Low leakage MOS targeted for low power
• Double-poly MOS for EPROM/Flash memories
• Triple well for isolation and leakage control
• Embedded memory are key components for System-on-chip
• SOI has many promising features, some design issues pending