Lecture 9: Combinational Circuits

Syed M. Mahmud, Ph.DECE Department

Wayne State University

Contents

• Decoders

• Encoders

• Multiplexers

• Implementing Boolean expression using Multiplexers

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Decoders

• Converts binary information from 𝑛 input lines to a maximum of 2𝑛

unique output lines.

• 𝑛-to-𝑚 decoder -> 𝑛 input lines, 𝑚 output lines where 𝑚 ≤ 2𝑛

• Practical circuit -> BCD to seven segment decoder

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Three-to-Eight Line Decoder

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Decoder with Enable

• Some decoders use NAND gates only

• For control of operation, an enable input is included.

• Decoder with Enable input can also be considered as a Demultiplexer• which receives inputs from a single line and directs it to one of the 2𝑛 output

lines.

• The selection of specific line is based on the input at the 𝑛 selection lines.

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2-to-4 Line Decoder with Enable• Here, we are using

active-low enable signal, meaning when E=0, the decoder will give valid outputs.

• Also the outputs are shown in negative logic, meaning the signal on selected output line is 0 and all others are 1.

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Larger Decoder Circuits• 4 × 16 decoder can be constructed using two 3 × 8 decoders.

• Here, we are using active-high enable, meaning when E=1 the outputs of the decoder will be valid. The outputs are shown in positive logic, meaning the signal on the selected output line is 1 and all others are 0.

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Combinational Logic Implementation

• Full Adder Implementation

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Encoders

• Inverse operation of a decoder.• Encoder has 2𝑛 or fewer input lines and 𝑛 output lines.

• If two or more inputs are active simultaneously, the output will produce an undefined combination.

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Priority Encoder

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Multiplexers• Selecting binary information from one of many input lines and directs

it to a single output line.

• Two-to-One line (2 × 1) Multiplexer

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Four-to-One Line Multiplexer

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Boolean Function Implementation

• 𝐹 = Σ 1,3,4,11,12,13,14,15• Using 16 × 1 multiplexer

• Using 8 × 1 multiplexer

• Using 4 × 1 multiplexer

• Using 2 × 1 multiplexer

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Boolean Function Implementation

• 𝐹 = Σ 1,3,4,11,12,13,14,15 using 8 × 1 multiplexer

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Combining MUXs

• Design a 8 × 1 MUX using 4 × 1 MUX and 2 × 1 MUX

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Further Reading

• 4.12 – HDL Models of Combinational Circuits• Gate level modeling

• Hierarchical Modeling

• Number representation

• Dataflow Modeling

• 4.13 – Behavioral Modeling

• 4.14 – Writing Sample Test bench

• 4.15 – Logic Simulation

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Summary

• How to design a decoder?

• How to implement logic circuits using decoder?

• What is priority encoder?

• How to design a multiplexer?

• How to implement logic circuits using multiplexer?

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Homework – 4 – Part b

• 4.23

• 4.26

• 4.28

• 4.31

• 4.33

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