Elementary Combinational Circuits

Elementary Combinational Circuits

Introduction

Combinational circuits are built from logic gates

Can realize arbitrary logical functions

Goal is to design efficient circuits

Also must keep in mind “extra-logical” properties

AB

C

D


Gate

Name

Symbol Truth Table P1 P1'

NOT

0 1

1 0

P1 P2 P1 + P2

OR

0 0 1 1

0 1 0 1

0 1 1 1

P1 P2 P1 P2

AND

0 0 1 1

0 1 0 1

0 0 0 1

P1 P2 P1 NAND P2

NAND

0 0 1 1

0 1 0 1

1 1 1 0

P1 P2 P1 NOR P2

NOR

0 0 1 1

0 1 0 1

1 0 0 0

P1 P2 P1 XOR P2

XOR

0 0 1 1

0 1 0 1

0 1 1 0

AB

C

D

Gates and corresponding truth tables


Gates perform the indicated logical transformation But, can also look at gates as filters acting on data streams

If control signal is 1, then AND gate will let signal pass through,If control signal is 0, then output is always 0

If control signal is 1, then OR gate produces 1If control signal is 0, then output is signal

?

AB

C

D

c tr ls ig n a l

c tr ls ig n a l

c tr ls ig n a l


Circuits to functions

Circuit equivalent to:

AB

C

D

PQ

R

PQ

R

(() + ())

((P NAND Q) + ())

((P NAND Q) + (R'))


Circuits to functions (cont.)

AB

C

D

AB

C

D

2) ((() () ())' XOR ())

1) (() XOR ())

3) (((A + B) (C) (D'))' XOR ())

4) (((A + B) (C) (D'))' XOR (CD))


Circuits to truth tables (directly)

AB

C

D

PQ

R

0 0 0 0 11 1 10 0 11 0 0 11

0 0 0 0 0 0 11

0 1 0 1 0 1 0 1

1 0 1 0 1 0 1 0

11 1 1 1 1 0 0

11 1 1 1 1 1 0


Functions to circuits (direct)

AB

C

D

X O R

N A N D *

C D+

A B

C D '

+

XO

R

NA

ND

*

CD

'C

D

AB

[(A + B)(C)(D')]' XOR [CD]

AB

C

D


Functions to circuits (through minterms)

AB

C

D

P Q R (PQ)' + R' minterm maxterm

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 0

P'Q'R' P'Q'R P'QR' P'QR PQ'R' PQ'R PQR' PQR

P + Q + R P + Q + R' P + Q' + R P + Q’ + R' P' + Q + R P' + Q + R' P' + Q' + R P' + Q’ +R'

(P'Q'R' + P'Q'R + P'QR' + P'QR + PQ'R' + PQ'R + PQR')

P

Q

R


Functions to circuits (through maxterms)

AB

C

D

P Q R (PQ)' + R' minterm maxterm

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 0

P'Q'R' P'Q'R P'QR' P'QR PQ'R' PQ'R PQR' PQR

P + Q + R P + Q + R' P + Q' + R P + Q’ + R' P' + Q + R P' + Q + R' P' + Q' + R P' + Q’ +R'

(P' + Q' + R')

PQR


NAND and NOR representations of SOP and POS circuits

1) step 1 justification bubbles cancel

2) step 2 justification generalized DeMorgan

AB

C

D

S u m of Produ cts Produ ct o f S u m s

1

2

1

2


Realizing minimal circuits

AB

C

D

C D0 1 1 1 1 0

0 0

0 1

1 1

1 0

2

1

1

1

111

1

1

11 C '

A'B'D '

0 0A B

[(A + B)(C)(D')]' XOR [CD]

C

ABD

ABCD(0,1,2,4,5,8,9,12,13)

A

B

C

D

A BC D

0 0 0 1 1 1 1 0

0 0

0 1

1 1

1 0

1

1

1

111

1

1

11

2 3

( C ' + D ')

( B' + C ') ( A ' + C ')

ABCD(3,6,7,10,11,14,15)


Gates and Integrated Circuits (IC’s) in practiceLogic families

AB

C

D

Technology Date

Relays 1930’s

Vacuum Tubes 1940’s-1950’s

TTL IC’s 1960’s-1990’s

CMOS IC’s 1990’s-present


Gates and Integrated Circuits (IC’s) in practiceValues and voltages

Binary Ternary

AB

C

D

u n de f in e d

H igh N o is eM argin

L o w N o is eM argin

0 .7 V C C

V C C

0 .3 V C C

0

V O H m in

V IH m in

V IL m ax

V O L m ax

V C C

0

u n de f in e d

u n de f in e d

L o w M a r gin

M iddle M a r gin

H igh M a r gin


Gates and Integrated Circuits (IC’s) in practiceFan-in and fan-out

Fan in is limited for CMOS gatesWorkaround

Propagation time proportional to fan-outsoft and hard constraints

AB

C

D

(ABC)' + (DEF)' ≡ (A' + B' + C' + D' + E' + F') ≡ (ABCDEF)'


Gates and Integrated Circuits (IC’s) in practiceGate delays

i) rise and fall times not instantaneousii) outputs lag inputsii) tpLH not in general equal to tpHL

AB

C

D

V IN

V O U T

tp L Htp H L

t im e

lo w v o lt a ge

h igh v o lt a ge

lo w v o lt a ge

h igh v o lt a ge


Gates and Integrated Circuits (IC’s) in practiceTransistor implementation of gates

NAND gate AND gate

AB

C

D

p -ch an n el

p -ch an n el

n -ch an n el

n -ch an n el

V D D

o u t

in 1(lo w )

in 2(lo w )

p -ch an n el

p -ch an n el

n -ch an n el

n -ch an n el

V D D

in 1(lo w )

in 2(lo w )

o u t

p -ch an n el

n -ch an n el

in verter


Summary of topicsGatesGates as filtersCircuits to functionsCircuits to truth tablesFunctions to circuits (direct)Functions to circuits through minterms and maxtermsNAND and NOR realizations of SOP and POS functionsGates and circuits in practice

Logic familiesValues and voltagesFan-in and fan-outGate delaysTransistor implementations of gates

AB

C

D

Elementary Combinational Circuits

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