VHDL Combinational Circuits

7/27/2019 VHDL Combinational Circuits

1/24

VHDL Fundamentals

Roveena RebelloNITK, Surathkal


2/24

1 Bit Equality Comparator

Inputs Output

A B AeqB

0 0 1

0 1 0

1 0 0

1 1 1

library ieee;

use ieee.std_logic_1164.all;

entity compare1 is

port(A,B: in std_logic;

AeqB: out std_logic);

end compare1;

architecture behavior of compare1 is

begin

process(A,B)

begin

AeqB


3/24

If the default assignment statement is removed:

process(A,B)

begin

if A=B then AeqB


4/24

E.g.: Heater Thermostatentity thermostat is

port(desired_temp, actual_temp: in integer;

heater_on: out boolean);

end entity;

architecture temp of thermostat is

begin

controller: process(desired_temp, actual_temp)

begin

if actual_temp


5/24

CASE Statement If behavior is to depend on the value of a single expression,

we can use case statement

General form:CASE expression IS

WHEN constant_value1=>

statement1;

WHEN constant_value2=>

statement1;

WHEN OTHERS=>

statement3;

END CASE;


6/24

8:1 Multiplexer using case staementlibrary ieee;


entity mux8 is

port(X: in std_logic_vector(7 downto 0);

sel: in bit_vector(1 downto 0);y: out std_logic);

end mux8;

architecture multiplexer of mux8 is

begin

process(X,sel)

begincase sel is

when 000=> y y y y y y y y


7/24

3 to 8 decoder using case statementlibrary ieee;


entity decoder1 is

port(a: in integer range 0 to 7;

y: out std_logic_vector(7 downto 0));

end dec3to8;

architecture dec3to8 of decoder1 is

begin

process(a)

begincase a is

when 0=> y y y y y y y y


8/24

3-8 decoderlibrary ieee;


entity decoder2 is

port(a: in integer range 0 to 7;

y: out std_logic_vector(7 downto 0));

end decoder2;

architecture dec3to8 of decoder2 is

begin

process(a)

beginy


9/24

WAIT Statement process cannot have sensititvity list when WAIT

statement is employed

3 types:1.syntax (WAIT UNTIL)

WAIT UNTIL signal_condition ;

E.g.: WAIT UNTIL A=B;

WAIT UNTIL clkevent and clk=1;2. syntax (WAIT ON)

WAIT ON signal1,signal2,;

E.g.: WAIT ON clk,rst;

3. syntax (WAIT FOR)WAIT FOR time_expression;

E.g.: WAIT FOR 5ns;


10/24

Possible modes for signals that are entity ports

Mode Purpose

IN Used for a signal that is an input to an entity

OUT Used for a signal that is an output from an entity. The value of

the signal cannot be used inside the entity. This means that in an

assignment statement, the signal can appear only to the left of

the


11/24

Entity with GENERICS Using generate statement: instantiate 4 copies of 1-bit adder

To make the code more general we can use GENERIC

statement

E bi f ll dd


12/24

E.g.: n-bit full adderlibrary ieee;


entity adder_n is

generic(n: integer:=4);

port(Cin: in std_logic;

X, Y:in std_logic_vector(n-1 downto 0);

S: out std_logic_vector(n-1 downto 0);

Cout: out std_logic);

end adder_n;

architecture structure of adder_n iscomponent fulladd

port(Cin,x,y: in std_logic;

Sum, Cout: out std_logic);

end component;

signal c: std_logic_vector(0 to n);

beginc(0)


13/24

8:1 multiplexer using generic statement

library ieee;


entity mux_m isgeneric(m: integer:=8);

port(X:in std_logic_vector(m-1 downto 0);

sel: in integer range 0 to m-1;

y: out std_logic);

end mux_m;

architecture structure of mux_m is

begin

process(sel,X)

beginy


14/24

16:1 multiplexer using generic statementlibrary ieee;


entity mux_m isgeneric(m: integer:=16);

port(X:in std_logic_vector(m-1 downto 0);

sel: in integer range 0 to m-1;

y: out std_logic);

end mux_m;

architecture structure of mux_m is

begin

process(sel,X)

beginy


15/24

Propagation DelayE.g.: C


16/24

Variables, Signals and ConstantsVariables:

Used for local storage in processes, procedures and functions

variable list_of_variable_names: type_name [:= initial_value];

Must be declared within the process in which they are used

They are local to that process

Signals:

Must be declared outside of a process

Signals declared at the start of an architecture can be used

anywhere within that architecture

signal list_of_signal_names: type_name [:= initial_value];


17/24

Constants:

constant constant _name: type_name:= constant _value;

Constants declared at the start of an architecture can be usedanywhere within that architecture

Constants declared within a process are local to that process

Signal updation using signal assignment statement:

signal _name:= expression [after dealy]; Signal is scheduled to change after the delay

If no delay specified then the signal is scheduled to beupdated after a delta delay

Variable updation using variable assignment statement:

variable_name:= expression;

Variable is instantaneously updated with no delay, not even adelta delay

P i i bl


18/24

Process using variablesentity test1 is

end test1;

architecture var of test issignal trigger, sum: integer:=0;

begin

process

variable var1: integer:=1;

variable var2: integer:=2;variable var3: integer:=3;

begin

wait on trigger;

var1:= var2+var3;

var2:= var1;

var3:= var2;

sum


19/24

Process using signalsentity test2 is

end test2;

architecture sig of test issignal trigger, sum: integer:=0;

signal sig1: integer:=1;



beginprocess

begin

wait on trigger;

sig1:= sig2+sig3;

sig2:= sig1;

sig3:= sig2;

sum


20/24

Arrays First declare an array type and then declare an array object

type SHORT_WORD is array(15 downto 0) of bit

Declares an array of type SHORT_WORD having an integerindex with a range from 15 downto 0 with each element in

the array of type bit

signal data_word:SHORT_WORD;

variable alt_word: SHORT_WORD:=0101010101010101;constant one_word: SHORT_WORD:= (others=>1);

Can access each bit of the array E.g.: alt_word(0)

Can specify a portion of the array E.g.: alt_word(5 downto 0)

General form for array type and array object declaration:

type array_type_name is array index_range of element_type;

signal array_name: array_type_name [:=initial_value];


21/24

Two-dimensional arrays

type matrix4x3 is array (1 to 4, 1 to 3) of integer;

variable matrixA: matrix4x3:=((1,2,3),(4,5,6),(7,8,9),(10,11,12));

matrixA initialised to 1 2 3

4 5 6

7 8 9

10 11 12

matrixA(3,2) refers to the element in 3rd row and 2nd column

Unconstrained array type: Dimension of the array may be

undefined

type intvec is array(natural range ) of integer

Range must be specified when the array object is declared

signal intvec5: intvec(1 to 5) := (3,2,6,8,1);


22/24

Two-dimensional array with unconstrained row and column

index range

type matrix is array( natural range , natural range ) ofinteger;

b


23/24

Prime Number Detector

Dataflow model

Structural model

Behavioral model

P i N b D t t i l t d


24/24

Prime Number Detector using selected

signal assignment (N is 4 bits)entity prime is

port(N: in std_logic_vector(7 downto 0);

y: out std_logic);

end prime;

architecture detector of prime isbegin

with N select

y

VHDL Combinational Circuits

Documents

Transcript of VHDL Combinational Circuits