Ch 3. Digital Circuits

3.1 Logic Signals and Gates

N bits can represent states (When N=1, 2 states)

– Black-box representation and Truth table shows a logic circuit with input/output and ignores electrical behavior of the circuit

Black-box

Input Output

– AND gate produces ‘1’ : Only if all of its inputs are ‘1’

– OR gate produces ‘1’ : One or more of its inputs are ‘1’

– NOT gate produces an output that is opposite of its input value

– NAND Gate : Opposite of an AND gate’s output

– NOR Gate : Opposite of an OR gate’s output

Black-box representation Truth table

– Timing diagram show how the circuit might respond

to a time-varying pattern of input signals

Lag

𝑿𝒀 +𝑿 ′𝒀 ′ 𝒁 ′

LagLag

Input

Output

3.3 CMOS Logic

Not expected to occur except during signal transition

High resistance : “Off” Transistor

Low resistance : “On” Transistor

NMOS

PMOSTurn on when

Turn on when

NMOS, Turn on when

PMOS, Turn on when

PMOS

NMOS

PMOS

NMOS

CMOS inverter

둘 중 하나만 On 되어도 Z=‘1’

둘 다 On 되어야 Z=‘0’

PMOS

NMOS

PMOS

NMOS

PMOS

NMOS

둘 중 하나만 On 되어도 Z=‘0’

둘 다 On 되어야 Z=‘1’

==

=

PMOS 는 F 를 이용

NMOS 는 F’ 를 이용

D

F

AND -> Series

OR -> Parallel

PMOS 는 F 를 이용

NMOS 는 F’ 를 이용

F =

F’ =

F

A

C

A

B

B

D

C

D

𝑽 𝒅𝒅

AND -> Series

OR -> Parallel

PMOS 는 F 를 이용

NMOS 는 F’ 를 이용

Inverter + Inverter

𝑨′𝑨

NAND + Inverter

𝑨 ∙𝑩𝑨 ∙𝑩

More Transistors are needed than NAND

𝑨 ∙𝑩+𝑪 ∙𝑫

(𝑨+𝑩) ∙(𝑪+𝑫)

4x3+2 =14 Transistor

6 Transistor

6 Transistor

4 Transistor

16 Transistor

≡

(𝑨+𝑩) ∙(𝑪+𝑫)

𝑨 ∙𝑩+𝑪 ∙𝑫

4x3+2 =14 Transistor

6 Transistor

4 Transistor

6 Transistor

16 Transistor

≡

3.4 Electrical Behavior of CMOS Circuits

3.5 CMOS Static Electrical Behavior

Noise can be added in signals

So, There are noise margins

: Min output voltage produced in high state

: Min input voltage guaranteed to be recognized as high

: Max input voltage guaranteed to be recognized as low

: Max output voltage produced in low state

High state 에서는 Minimum value 고려

Low state 에서는 Maximum value 고려

𝑽 𝑻𝒉𝒆𝒗=𝟐𝒌𝞨

𝟐𝒌𝞨+𝟏𝒌𝞨×𝟓𝑽=𝟑 .𝟑𝑽

Not CMOS resistive load

𝑽 𝑻𝒉𝒆𝒗=𝟏𝟎𝟎𝞨

𝟏𝟎𝟎𝞨+𝟔𝟔𝟕𝞨×𝟑 .𝟑𝟑𝑽=𝟎 .𝟒𝟑𝑽

When

𝑽 𝑻𝒉𝒆𝒗=(𝟓𝑽 −𝟑 .𝟑𝟑𝑽 ) 𝟐𝟎𝟎𝞨𝟐𝟎𝟎𝞨+𝟔𝟔𝟕𝞨

+𝟑 .𝟑𝟑𝑽=𝟒 .𝟔𝟏𝑽

When

𝑽 𝒊𝒏=𝟎 .𝟎𝑽

𝑹𝒏 ( 𝒐𝒏)≅𝑽 𝑶𝑳𝒎𝒂𝒙𝑻

𝑰𝑶𝑳𝒎𝒂𝒙𝑻

𝑹𝒑 (𝒐𝒏 )≅𝑽 𝑫𝑫−𝑽 𝑶𝑯𝒎𝒊𝒏𝑻

|𝑰 𝑶𝑯 𝒎𝒂𝒙𝑻|(TTL load) (TTL load)

𝑽 𝒊𝒏=𝟓 .𝟎𝑽

𝑰𝒐𝒖𝒕=𝟑 .𝟑𝟑𝑽

𝟎 .𝟔𝟔𝟕𝒌𝞨=𝟓.𝟎𝒎𝑨 |𝑰𝒐𝒖𝒕|=

𝟓 .𝟎𝑽 −𝟑 .𝟑𝟑𝑽𝟎 .𝟔𝟔𝟕𝒌 𝞨

=𝟐 .𝟓𝒎𝑨

Sink current Source current

𝒁=𝑿 ∙ 𝑿=𝑿

Pull-up Pull-down

𝒕𝒓 𝒕 𝒇

No Transition Time in ideal case

(20% ~ 80%) (80% ~ 20%)

3.6 CMOS Dynamic Electrical Behavior

Both the speed and the power consumption of a CMOS device depend to a large extent on “AC” device

High State Low State

𝑽 𝑶𝑼𝑻=𝑽 𝑫𝑫 ∙𝒆−𝒕

𝑹𝒏 𝑪𝑳

𝒕 𝒇 =−𝑹𝒏𝑪 𝑳 ∙ 𝒍𝒏𝑽 𝑶𝑼𝑻

𝑽 𝑫𝑫

Low State High State

𝑽 𝑶𝑼𝑻=𝑽 𝑫𝑫 ∙(𝟏−𝒆−𝒕

𝑹𝒑 𝑪𝑳 )

𝒕𝒓=−𝑹𝑪 ∙ 𝒍𝒏𝑽 𝑫𝑫−𝑽 𝑶𝑼𝑻

𝑽 𝑫𝑫

50%50%

Ideal case (No rise and fall times)

Propagation delay

(internal power dissipation due to output transition)

(Power due to load capacitor)

𝑷𝑫=𝑷𝑻 +𝑷 𝑳= (𝑪𝑷𝑫+𝑪𝑳 ) ∙𝑽 𝑪𝑪𝟐 ∙ 𝒇 =𝑪𝑽 𝟐 𝒇

𝒊𝒇 𝑽 𝑰𝑵𝟏 ,𝑽 𝑰𝑵𝟐 ,⋯ ,𝑽 𝑰𝑵𝟖=𝑳 ,𝒕𝒉𝒆𝒏𝒂𝒍𝒍𝟖𝑽 𝒐𝒖𝒕=𝑯𝒊𝒇 𝑽 𝑰𝑵𝟏 ,𝑽 𝑰𝑵𝟐 ,⋯ ,𝑽 𝑰𝑵𝟖=𝑯 ,𝒕𝒉𝒆𝒏𝒂𝒍𝒍𝟖𝑽 𝒐𝒖𝒕=𝑳

𝟔𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓

𝑺′

XS

YS＇

𝟏𝟐𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓

3.7 Other CMOS input and Output Structures

𝟓 .𝟎𝑽 →𝟐 .𝟒𝑽 : 𝑳𝒐𝒘𝟎 .𝟎𝑽→𝟐 .𝟒𝑽 :𝑯𝒊𝒈𝒉

𝑺𝒕𝒂𝒕𝒆𝒂𝒕𝟐 .𝟒𝑽𝒐𝒍𝒕𝒂𝒈𝒆

𝑺𝒄𝒉𝒎𝒊𝒕𝒕−𝒕𝒓𝒊𝒈𝒈𝒆𝒓 𝒊𝒏𝒗𝒆𝒓𝒕𝒆𝒓

Open-drain output requires an external pull-up resistor

Increase because R=1.5K𝞨Pull-up Resistor

𝑹=𝑽 𝑪𝑪−𝑽 𝑶𝑳−𝑽 𝑳𝑬𝑫

𝑰𝑳𝑬𝑫=𝟓 .𝟎−𝟎 .𝟑𝟕−𝟏 .𝟔

𝟏𝟎𝒎𝑨≈𝟑𝟎𝟑𝞨

𝑶𝒕𝒉𝒆𝒓𝒔=𝑳

(AND Function)

X

Y

W

Burn !

𝑰 𝑶𝑳𝒎𝒂𝒙=𝟒𝒎𝑨 (𝑨𝒔𝒔𝒖𝒎𝒑𝒕𝒊𝒐𝒏)

𝑰 𝑹𝒎𝒂𝒙=𝟒− (𝟐 ∙𝟎 .𝟒 )=𝟑 .𝟐𝒎𝑨

Low output must sink 0.4mA

𝑰 𝑰𝑳𝒎𝒂𝒙=−𝟎 .𝟒𝒎𝑨

R𝒎𝒊𝒏=𝟓 .𝟎−𝟎 .𝟎

𝑰𝑹𝒎𝒂𝒙

=𝟏𝟓𝟔𝟐 .𝟓𝞨

𝑽 𝑶𝑳=𝟎 .𝟎𝑽 ( 𝑨𝒔𝒔𝒖𝒎𝒑𝒕𝒊𝒐𝒏)

In high state, typical open-drain outputs have a maximum leakage current 5uA and typical LS-TTL inputs require 20uA of a source current

𝑰 𝑹𝒍𝒆𝒂𝒌=(𝟒 ∙𝟓𝒖𝑨 )+(𝟐 ∙𝟐𝟎𝒖𝑨)=𝟔𝟎𝒖𝑨𝞨

𝑰 𝑰𝑯𝒎𝒂𝒙=𝟐𝟎𝒖𝑨❑

3.8 CMOS Logic Families

High-speed CMOS High-speed CMOS, TTL compatible

3.9 Low-Voltage CMOS Logic and Interfacing

𝑷𝑫=𝑷𝑻 +𝑷 𝑳= (𝑪𝑷𝑫+𝑪𝑳 ) ∙𝑽 𝑪𝑪𝟐 ∙ 𝒇 =𝑪𝑽 𝟐 𝒇

Clamp overshoot

Clamp diode

To Clamp overshoot

Clamp undershoot

0.6V

-0.6V

G

G

S

D

S

OFF

OFF

S

D

G

S

D

𝑾𝒉𝒆𝒏𝑽 𝒐𝒖𝒕>𝑽𝒄𝒄 ,𝑸𝟑=𝑶𝑵

D

3.10 Bipolar Logic

AND

pnp

𝑵𝒐𝒕 𝒅𝒆𝒆𝒑𝒍𝒚 𝒔𝒂𝒕𝒖𝒓𝒂𝒕𝒆𝒅

𝟎 .𝟐𝟓𝑽

Diode AND Gate

Output stage= Totem pole

V

Phase Splitter

Path for discharging both

𝑳𝒐𝒘

𝑯𝒊𝒈𝒉

𝟎 .𝟕𝑽

𝟎 .𝟑𝑽1

𝑪𝑴𝑶𝑺

𝑻𝑻𝑳𝑪𝑴𝑶𝑺

𝑻𝑻𝑳

𝑻𝑻𝑳