Cs2100 4 Logic Gates and Circuits

CS2100 Computer Organisation

Logic Gates and Circuits


AY11/12 Sem 1Logic Gates and Circuits*LOGIC GATES AND CIRCUITSGate SymbolsInverter/AND/OR/NAND/NOR/XOR/XNORDrawing and Analysing Logic CircuitsUniversal GatesSOP and NAND CircuitsPOS and NOR CircuitsProgrammable Logic Array


AY11/12 Sem 1Logic Gates and Circuits*LOGIC GATESGate symbols


AY11/12 Sem 1Logic Gates and Circuits*INVERTER/AND/OR GATESInverter (NOT gate)AND gateOR gate

AA'01

ABA B00011011

ABA + B00011011


AY11/12 Sem 1Logic Gates and Circuits*NAND GATENAND gate

AB(A B)'00011011


AY11/12 Sem 1Logic Gates and Circuits*NOR GATENOR gate

AB(A + B)'00011011


AY11/12 Sem 1Logic Gates and Circuits*XOR GATEXOR gate

ABA B00011011


AY11/12 Sem 1Logic Gates and Circuits*XNOR GATEXNOR gateXNOR can be represented by (Example: A B)

AB(A B)'00011011


AY11/12 Sem 1Logic Gates and Circuits*LOGIC CIRCUITS (1/2)Fan-in: the number of inputs of a gate.Gates may have fan-in more than 2.Example: a 3-input AND gateGiven a Boolean expression, we may implement it as a logic circuit.Example: F1 = xyz' (note the use of a 3-input AND gate)


AY11/12 Sem 1Logic Gates and Circuits*LOGIC CIRCUITS (2/2)Example: F2 = x + y'zExample: F3 = xy' + x'z


AY11/12 Sem 1Logic Gates and Circuits*ANALYSING LOGIC CIRCUITSGiven a logic circuit, we can analyse it to obtain the logic expression.Example: Given the logic circuit below, what is the Boolean expression of F4?F4 = ?


AY11/12 Sem 1Logic Gates and Circuits*QUICK REVIEW QUESTIONS (1)DLD page 77 Questions 4-1 to 4-4.


AY11/12 Sem 1Logic Gates and Circuits*UNIVERSAL GATESAND/OR/NOT gates are sufficient for building any Boolean function.We call the set {AND, OR, NOT} a complete set of logic.However, other gates are also used:Usefulness (eg: XOR gate for parity bit generation)EconomicalSelf-sufficient (eg: NAND/NOR gates)


AY11/12 Sem 1Logic Gates and Circuits*NAND GATE{NAND} is a complete set of logic.Proof: Implement NOT/AND/OR using only NAND gates.(xx)' = x' (idempotency)((xy)'(xy)')' = ((xy)')' (idempotency) = xy (involution)((xx)'(yy)')' = (x'y')' (idempotency) = (x')'+(y')' (DeMorgan) = x+y (involution)


AY11/12 Sem 1Logic Gates and Circuits*NOR GATE{NOR} is a complete set of logic.Proof: Implement NOT/AND/OR using only NOR gates.(x+x)' = x' (idempotency)((x+y)'+(x+y)')' = ((x+y)')' (idempotency) = x+y (involution)((x+x)'+(y+y)')' = (x'+y')' (idempotency) = (x')'(y')' (DeMorgan) = xy (involution)


AY11/12 Sem 1Logic Gates and Circuits*QUICK REVIEW QUESTIONS (2)DLD page 77 Questions 4-6 to 4-8.


AY11/12 Sem 1Logic Gates and Circuits*SOP AND NAND CIRCUITS (1/2)An SOP expression can be easily implemented using2-level AND-OR circuit2-level NAND circuitExample: F = AB + C'D + EUsing 2-level AND-OR circuit


AY11/12 Sem 1Logic Gates and Circuits*SOP AND NAND CIRCUITS (2/2)Example: F = AB + C'D + EUsing 2-level NAND circuit


AY11/12 Sem 1Logic Gates and Circuits*POS AND NOR CIRCUITS (1/2)A POS expression can be easily implemented using2-level OR-AND circuit2-level NOR circuitExample: G = (A+B) (C'+D) EUsing 2-level OR-AND circuit


AY11/12 Sem 1Logic Gates and Circuits*POS AND NOR CIRCUITS (2/2)Example: G = (A+B) (C'+D) EUsing 2-level NOR circuit


AY11/12 Sem 1Logic Gates and Circuits*READING ASSIGNMENTPropagation DelayRead up DLD section 4.5, pg 69 71.Integrated Circuit Logic FamiliesRead up DLD section 4.6, pg 71 72.


AY11/12 Sem 1Logic Gates and Circuits*INTEGRATED CIRCUIT (IC) CHIPExample of a 74LS00 chip: Quad NAND gates.


AY11/12 Sem 1Logic Gates and Circuits*PROGRAMMABLE LOGIC ARRAYA programmable integrated circuit implements sum-of-products circuits (allow multiple outputs).2 stagesAND gates = product termsOR gates = outputsConnections between inputs and the planes can be burned.


AY11/12 Sem 1Logic Gates and Circuits*PLA EXAMPLE (1/2)


AY11/12 Sem 1Logic Gates and Circuits*PLA EXAMPLE (2/2)Simplified representation of previous PLA.


AY11/12 Sem 1Logic Gates and Circuits*READ ONLY MEMORY (ROM)Similar to PLASet of inputs (called addresses)Set of outputsProgrammable mapping between inputs and outputsFully decoded: able to implement any mapping.In contrast, PLAs may not be able to implement a given mapping due to not having enough minterms.


AY11/12 Sem 1Logic Gates and Circuits*END


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Cs2100 4 Logic Gates and Circuits

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