Boolean Low Power Logic Circuits with Reversible Gates

ISSN NO: 0745-6999 JOURNAL OF RESOURCE

MANAGEMENT AND TECHNOLOGY

Page No:122 Vol12, Issue2, 2020

Boolean Low Power Logic Circuits with Reversible Gates

1Rajkumar Jarpula

1Assistant Professor, Department of ECE,

Avanthi Institute of Engineering & Technology

Abstract—Low power design is a promising characteristic for the application ranging from the Internet of

things (IoTs) to quantum computing. The boolean logic based on the reversible concept is the emerging

technology for low power digital logic circuit design for quantum computing application. The reversible logic

circuit provides an entirely new way of processing quan-tum computing. In this paper,we present the

transistor level implementation of state-of-the-art reversible gates and proposed boolean logic circuits using

reversible logic gates. The various Boolean logic circuits based on reversible logic gates are designed using

the SCL180nm library. Furthers, we introduced D-flip flop and 4x1 MUX using the reversible gate, which

has an energy efficiency of 14% and 94%, respectively, with reported paper. This proposed logic circuits

achieved area efficiency as well as a power-efficiency because of reversible logic gates, which consume less

power due to its distinctive input-output mapping techniques.

Index Terms—Reversible computing; Low power design; re-versible logic,Quantum computing;

I. Introduction

Todays the application ranging from IoTs

to quantum com-puting require the energy-efficient

design of the digital circuit. So energy loss is one

of the parameters which should be considered

during Logic circuit design. From the past ten

years,the improvement in fabrication steps for more

number of integration chip has reduced heat

dissipation. The concept of reversible logic [1] has

acknowledged excessive use in low power digital

circuit design in the previous ten year due to their

capability to decrease the energy dissipation. The

reversible logic concept used by the following

applications ranging from low power digital design,

quantum computation, and nanotechnology.

Previously Irreversible logic concept used for

computation purposes, but it consumes more power

due to loss of information during computation [2].

Rolf Landauer et al. [2] calculate the amount of

energy dissipated for every irrepressible bit

operation, and the value of energy dissipation

according to Rolf Landauer is at least KT ln2

joules.

Bennett et al. [1] have proved that a KT ln2 amount

of energy will be saved from a system because of

the duplication of the inputs from detected outputs.

The energy dissipation can be suppressed or even

removed if computation without loss of in-

formation. The reversible digital logic supports

both backward and forward computation operations

inside the system. The outputs or intermediate

values of production can be computed from the

combinations of inputs or by only going back to the

computation history at any point. The impact of

reversibility and its scope on the current computer

industry or eventually in the VLSI industry can be

better understood by the figure 1. It was evident

that researchers have almost reached their limit in

terms of energy consumption. The point here is that

using the concept of reversibility. Further design

can be made if we are looking for new and more

toward energy-efficient models.

Figure 1: Scope of reversible computing

This paper structure is arranged as follows. Section

II briefly explains the literature review of reversible

logic and related work on reversible circuit design.

Part III describes the implementation of reversible

logic gates. Section IV explains the digital design

of the boolean logic circuit using reversible logic

gates. Experimental setup and results are reported

and discussed in Section V. Section VI summarizes




the work and presents scope for future work for the

same.

II. Literature review and Related Work A.

Reversible digital logic

Reversibility is a process whose direction can be

reversed at any time during computation when any

loss of data during computation, and there states, so

data can never be lost during computing. The

recovery of an earlier stage of calculation is made

by computing the results either backward or

forward direction; it is called logical reversibility.

Reversible logic computation has shown its distinct

feature of recovering the loss bit during a

calculation, the recovery of lost bit has to be done

by distinctive input-output mapping techniques,

where the conventional method of logic

computation has failed to recover the lost bit. The

benefit of logical reversibility can be further

extended if we employed physical reversibility

before it. The process in which no energy

dissipation translates to heat is called physical

reversibility. The perfect physical reversibility in

the computational system is not achievable. In

computing systems, when voltage levels shift (i.e.,

bits from zero to one) from High to Low, then

energy dissipate in terms of heat. This shifting

mechanism of voltage level needs a very less

amount of energy, and most of the power is

consuming in the form of heat. The charge

movement from one node to the next node would

be done progressively by the reversible circuit

element. In this way, there is a tiny loss of energy

for each transition. The current digital system

profoundly affected by the Reversibility concept.

The Reversibility concept recovered the inputs state

from the outputs, which also affects assembly

programming languages and instruction set. This is

so because these also need to be reversible to

provide optimal efficiency[13]. The idea of

reversibility and how it differs from irreversibly

has been shown in figure 2. It can be noted that if

we add something to the irreversible, the design

can be transformed into a reversible one.

Figure 2: Concept of reversible computing

(a)Irreversible logic,(b) Reversible logic

Some factors that we should considered for

designing of reversible circuits has been discussed

below.

Garbage Outputs(GO): The set of outputs that

remain unused during computation in a reversible

logic circuit called garbage output. These not

synthesized. In other word the extra sets of outputs

that are used to make the required circuit reversible

are known as garbage outputs.

Quantum cost (QC): It is the sum of all costs of

1X1 or 2X2 primitive gates present in the circuit.

Explicitly it is the cost of 1X1 NOT gate and 2X2

CNOT gate required to realize the reversible

circuit.

Ancilla Inputs(AI): The sets of inputs that are

maintained at constant value either logic ’0’ or

logic ’1’ to synthesize the given logical function

known as ancilla inputs or regular inputs.

There are few essential points in reversible digital

circuit design and synthesis when we talk about

systematical and efficient reversible design is

Minimization of quantum cost Minimization

garbage outputs Minimization of delay

Avoid constant inputs

Avoid fan-out by using copying gate.

B. Related Work

Reversible logic circuits are analogous to

conventional logic circuits barely; they are realized

using reversible logic gates. Reversible gates like

Feynman gate (2x2), Toffoli gate (2x2), Fredkin

gate (3x3), Sayem gate (4x4) and many more has

been already reported in the literature. The 1x1

NOT gate and 2x2 reversible logic gate can realize

any size of reversible logic gates. Non-dissipation

reversible gates can also use in optical computing.

German physicist Rolf Landure shown that for

every irreversible computation minimal amount of

energy, i.e., KTln2 joules dissipates for every one

bit of information lost. A detailed survey of

reversible gates discussed in [3]. Most popularly

used techniques for reversible circuit imple-

mentation constitute Charge recovery logic [14],

Split Level charge recovery logic, reversible energy

recovery logic [4] and NMOS recovery logic.

Further optoelectronic and nanometre based

implementation of reversible circuits is presented in




[5]. Garbage output minimization has been the

foremost chal-lenging issue while designing ant

type of reversible circuits.

[6] concludes reversible computations is also

related to other emerging research domain such as

quantum computing, optical computing, and

nanotechnology that also uses similar sets or some

transformed set of reversible gates. The first

dedicated implementation of reversible gates in

CMOS technology done in [7]. This work exploits

reuse of original signal energy and characterizes

adiabatic switching, which switches transistors in a

better efficient way[15]. SPICE simulation of

reversible circuits has shown such implementation

has the potential to reduce energy consumption by

a factor of 10. This implies that not all applications

are suitable for implementation using reversible

gates. The author in [8] presents optimized optical

logic gates for enhancement of the speed of the

integrated photonic circuit. The author in [9]

presents a 4-bit Johnson counter using reversible

logic gates.

III. Implementation of Reversible logic

gates

In this section, the transistor implementation of

reversible logic gates, which has the equal number

of input and output, all these inputs and outputs

have to map by its corresponding inputs and

outputs. The logic gate is called a reversible gate if

it gives the output vector from the input vector and

vice-versa. The reversible gate consumes energy in

a very efficient way. Due to its reversibility nature,

fan-out is not possible in reversible circuits, Fan-

out can be achieved by adding the additional gate

in this reversible circuit [6]. In this paper, we have

addressed basic reversible gates like Feynman gate,

Fredkin gate, Sayem gate, and their corresponding

dedicated transistor implementation. These kinds of

the application give rise to the standard building

blocks, which can be further used to design various

complex circuits reversibly[16]. Some of the

Boolean circuits have also been developed in this

paper by using reversible logic gates. The design

promises the main essence of reversible computing

that consumes very little power. The well-

recognized standard reversible gates and their

transistorized implementation has been discussed

below [10].

A. Feynman Gate

FG is a 2x2 reversible logic gate; its block diagram

and truth table are shown in figure 3(a) and 3(b),

respectively. The inputs are A, B, and the outputs

are P, Q. P=A gives the outputs of this gate, Q=A

B. The Quantum cost of an FG is calculated to be

1. Though fan-out is not used in reversible logic,

the FG gate cab is used for the duplication of the

desired net. The corresponding transistorized

implementation has been shown in figure 4., Where

eight CMOS transistor has been used in this design.

The below model can be used as an improved

EXOR gate with a reversibility feature. It can be

easily verified from the output waveform that

design works well for both forward and reverse

directions. Figure 5 shows the layout of the

Feynman gate.

Figure 3: Feynman gate (a)Feynman gate Block

Dia-gram,(b)Feynman gate Truth table

B. Fredkin Gate

Fredkin Gate(FrG) is a 3x3 reversible gate, its

block di-agram, and truth table are shown in Figure

6(a) and 6(b), respectively. It has inputs A, B, C,

and the outputs vector are P, Q, P=A defines

R.Output, Q=AB AC, and R=A’C

AB.The quantum cost of an FrG is calculated to be

five [4]. The corresponding transistorized

implementation has been shown in figure 7, which

contains two NMOS and two PMOS transistors. In

this implementation, the output P is taken directly

from input A and vice-versa[17]. The

implementation also requires two buffers at

remaining output terminals Q and R to condition

the required output signal. This implementation

works well in forward as well as backward

direction and thus fully reversible.

C. Sayem Gate

Sayem gate (SG) is a 4x4 reversible gate shown in

figure 9. The input and output vector of this gate is,

I(A, B, C, D) and




O (A, A’B EXOR AC, A’B EXOR AC EXOR D,

AB EXOR A’C EXOR D). The Sayem gate can be

used to build reversible standard sequential circuits

like T flip-flop, D flip-flop along with Feynman

gate. The corresponding implementation of Sayem

gate has been shown in figure 10. This gate

requires two Fredkin gate and one Fredkin gate. In

order to condition

Figure 4: Schematic of Feynman gate

Figure 5: Layout of Feynman gate

Figure 6: Fredkin Gate (a)Fredkin Gate Block Dia-

gram,(b)Fredkin Gate Truth table,

the output buffers are used here. This

implementation works suitable for both forward as

well as backward computations, i.e., completely

reversible and can be verified from the output wave

forms [5].

IV. Proposed Reversible Circuit design

A. Design of reversible Combinational

Circuit: 4 x 1 mux

A 4x1 mux has four inputs I(A, B, C, D), two select

lines S0, S1, and one output F. It works as the data

selector depending upon the states of choose lines.

The design has been implemented using four

Fredkin gates [5]. The diagram of reversible 4x1

mux has been shown below in figure 11.

Figure 7: schematic of Fredkin Gate

Figure 8: Layout of Fredkin Gate

Figure 9: Sayem Gate (a)Sayem Gate Block

Diagram,(b)Sayem Gate Truth table

border with cross mark represents the garbage

outputs and is unused in this case. The design

works well for both forward and reverses direction

computation [6].

B. Design of reversible Sequential Circuit:

D- Flip Flop

The D flip-flop is an essential memory element that

contains a single input and clock pulses and dual

output. The action of the D flip-flop is straight

forward. When the clock pulse transitions from low

to high, the value of D is transferred to Q. The




characteristic equation of D-Flip flop is q(+) =

De+eQ. D-flip flop can be the realization by using

a single Sayem gate is giving e, q, D, and 0

respectively in A, B, C, and D input of Sayem gate.

Figure 12 shows the design [1]of reversible D-Flip

Flop. D-Flip Flop with only Q output and Figure 12

shows the circuit schematic of reversible D-Flip

Flop with both the output present Q and next Q+.

One FG is used in D flip flop for producing copy

operation of the complement of Q from SG for the

design [10].

Table I: Performance metrics of Proposed Fredkin

gate

Figure 10: Sayem Gate schematic

Figure 11: 4X1 Mux using reversible gates

Figure 12: D-Flip Flop using reversible gate

V. Experimental Setup

The proposed reversible circuits have been

implemented in Spice using cadence virtuoso. The

reversible boolean logic circuits would consume

more power if they designed using conventional

gates for computations reversibly. It is essential to

replace the basic logic gates using reversible gates

in the reversible boolean logic circuit to get a

perfect reversible estimate, which is exciting and

challenging, both fact being known that a reversible

circuit must be reversible at every level of

abstraction. So in this paper, basic reversible gates

have been realized using Cadence Virtuoso

Schematic editor. Again these basic gates used to

recognize the reversible mux and reversible D-flip

flop circuits. The output waveforms have been

obtained after importing .csv file into Mat lab. The

layout work has been carried out in Cadence

Layout Suite XL Editing using the SCL 180nm

library.

Table II: Performance metrics of Proposed

Feynman gate

Figure 13: Simulation Result of Feynman Gate

(a)Forward Simulation, (b) Backward Simulation

VI. Result and discussion

The dedicated switch level implementation of

Feynman gate, Fredkin gate, and Sayem gate has

been done in this paper. The forward and backward

simulation results have been shown in figure [13-

15]. The reversibility can be verified using these

waveforms. Feynman gate in [1]and[3] can not

work in both directions, but the proposed design is

fully reversible. Table I shows that the proposed

Feynman gate has a 4% delay improvement and

99% reduction in energy consumption over [11];

this also has better energy efficiency than

conventional Feynman gate. Table II shows that the

proposed Fredkin gate has 50% area improvement

and 61 % power improvement over [11]. The




power consumption of Sayem gate found to be

1.4nw. Table III shows that D-FF using Sayem gate

has a 14% reduction in energy consumption over

[12]. Table IV shows that the design of 4x1 mux

using proposed Fredkin gates has 83% delay

improvement and a 94% reduction in energy

consumption over [13].

The proposed reversible gate shows a tremendous

decrease in power consumption, which is one of the

most significant advantages to use the concept of

reversibility. There is a substantial reduction in area

and gate count in the design of a combinational and

sequential circuit using reversible logic gates. The

reversible computing scope indicates that it will

have a prominent role in the VLSI circuit design

industry.

Figure 14: Simulation Result of Fredkin Gate (a)

Forward Simulation, (b) Backward Simulation

Figure 15: Simulation Result of Sayem

Gate:(a)Forward Sim-ulation,(b)Backward

Simulation

Figure 16: Simulation of proposed reversible D-flip

flop circuit

Figure 17: Simulation of proposed reversible 4X1

Mux circuit

VII. Conclusion

In this paper, the transistor level implementation of

primary reversible gate, i.e., Feynman Gate,

Fredkin Gate, Sayem Gate, have been carried out.

The simulation results of all reversible gates have

been verified for both forward and backward

computations. The transistor-level implementation




of Feynman gate and Fredkin gate also shows the

reduction of energy consumption of 99% and 23%

concerning conventional Feyn-man and Friedkin

gate. We have also introduced reversible circuits

(i.e., D-flip flop and 4X1 mux) using basic

reversible gates,which also show energy

improvement of 13.53% in D flip flop and 94% in

4X1 mux with respect to non reversible D flip flop

and 4x1 mux. The analysis part shows that the

design has lower power consumption, improved

delay, and provides a compact design. Hence low

power boolean logic circuit design using reversible

circuits is suitable for VLSI applications. Frequent

challenges in the design of complex reversible

circuits are the minimization of quantum cost and

garbage outputs, which need to be addressed in

future design problems.

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Boolean Low Power Logic Circuits with Reversible Gates

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