Chapter 14
Sequential logic, Latches and Sequential logic, Latches and FlipFlip--FlopsFlops
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2
Lesson 4
JK Flip Flop
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3
JK Flip-Flop – ve edge triggered• Output Q and Q
Q
Q
K
J
Q
QJ
K
SR LatchClock
Clock
-ve Edge triggered circuit
↓
R
SPreset
clear
PR CLR
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4
JK Flip-Flop + ve edge triggered• Output Qand Q
Q
Q
K
J
Q
QJ
K
JK FFClock
Clock
+ve Edge triggered circuit
↑
R
SPreset
clear
PR CLR
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5
JK Flip Flop
1. It has edge trigger clock input so that the output state changes only on a clock edge
2. The NANDs S input of level clocked SR latch labeled as J input and R input as K input.
3. Second input of both NANDs is common 4. Clock input has an additional circuitry to make
the J and K inputs transparent at an instance corresponding to an edge at the clock input
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6
JK Flip Flop� Three input cross coupled NANDs � Third input of lower NAND connects the Q
output� Third input of upper NAND connects the Q
output.� There is no unstable condition in J-K FF
state table
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7
Clock Symbolic representation• A bubble followed by a triangle at a clock
input represents negative edge triggered clock and output will correspond to the J and K inputs at that -ve edge instance only
• A triangle at a clock input represents positive edge triggered clock and output will correspond to the J and K inputs at that +ve edge instance only
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8
Clock edge Symbolic representation
• Down side arrow corresponds -ve edge instance (0 to 1 transition only)
• Up side arrow corresponds +ve edge instance (1 to 0 transition only)
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9
J = 0 and K = 0 No change state• Output Q remains same as before
even after the clock edge when J = 0 and K =0
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10
J = 0, K = 0
Inputs Output State
Clock Qn J Qn K Qn+1 Qn+1
X means either 1 or 0 or +ve edge or -ve edge input, Qn+1 means next state after nth clock input
X 0 0 1 0 Qn Qn No change
X 1 0 0 0 Qn Qn No change
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11
J = 1 and K = 0 (Q set to 1)• Output Q sets to 1 and Qn becomes =
0 after the clock edge when J = 1 and K =0
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12
J = 1, K = 0 -ve edge triggered JK
Inputs Output State
Clock Qn J Qn K Qn+1 Qn+1
X means either 1 or 0 input, Qn+1 means next state after nth clock input
1 0 1 1 0 Qn Qn No change
0 1 1 0 0 Qn Qn No change
↑ X 1 X 0 Qn Qn No change
↓ X 1 X 0 1 0 Sets to 1
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 13
J = 0 and K = 1 (Q reset to 1)• Output Q resets to 0 and Qn becomes
= 1 after the clock edge when J = 0 and K = 1
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14
J = 0, K = 1 -ve edge triggered JK
Inputs Output State
Clock Qn J Qn K Qn+1 Qn+1
X means either 1 or 0 input, Qn+1 means next state after nth clock input
1 0 0 1 1 Qn Qn No change
0 1 0 0 1 Qn Qn No change
↑ X 0 X 1 Qn Qn No change
↓ X 0 X 1 0 1 Resets to 0
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 15
J = 1 and K = 1 (Q Toggles)• Output Q resets to 0 and Qn becomes = 1
in case Q was 1 earlier Qn was 0 and after the clock edge when J = 1 and K = 1
• Output Q sets to 1 and Qn becomes = 0 in case Q was 0 earlier Qn was 1 and after the clock edge when J = 1 and K = 1
• Q toggles (complements the nth state after the nth clock transition)
• Qn+1 ← Qn
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 16
J = 1, K = 1 -ve edge triggered JK
Inputs Output State
Clock Qn J Qn K Qn+1 Qn+1
X means either 1 or 0 input, Qn+1 means next state after nth clock input
1 0 1 1 1 Qn Qn No change
0 1 1 0 1 Qn Qn No change
↑ X 1 X 1 Qn Qn No change
↓ 1 1 Qn Qn Toggles
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 17
Use of Clear and Preset Inputs
• JK FF may have connections to the two inputs of cross coupled NANDs. It can be used as R (clear) and S (preset), to preset Q to 1 or to reset Q to 0.
Summary
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 19
We learnt that in JK edge triggered FF: • When J = 1 and K =1, the output of flip-flop
toggles (changes to opposite state) on clock edge.
• When J = 0 and K =0, the output of flip-flop does not change on clock edge.
• When J = 0 and K =1, the output Q resets to 0 after clock edge.
• When J = 1 and K =0, the output Q sets to 1 after clock edge
End of Lesson 4 on
JK Flip Flop
Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 21
THANK YOU
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