CENT-113 Digital Electronics1
Flip Flops• TI Type 502 Flip Flop: 1st production IC in 1960.
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Interest• 1919: W. H. Eccles and F. W. Jordan publish the first
flip-flop circuit design.• M74HC74AM Fairchild CMOS flip-flop for frequency
manipulation is used in a Smart Card Reader.
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Logic Circuit Classifications• Combination Logic Circuits
– Building block is the logic gate.– Use AND, OR, NOT gates.
• Sequential Logic Circuits– Building block is the flip flop (FF).– Used in timing and memory devices.– Flip Flops are wired to form counters, shift registers,
and various memory devices.
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R-S Flip Flop• Logic Symbol Wiring Diagram
Set
Reset Complementary
NormalS
R
Q
Q
FF
• Truth Table Waveform DiagramMode of
OperationInput
SInput
ROutput
QOutput
QEffect
Prohibited 0 0 1 1 ProhibitedDo not use
Set 0 1 1 0 For settingQ to 1
Reset 1 0 0 1 ResettingQ to 0
Hold 1 1 Q Q DependsPrevious
State
Input Output
Input
Output
Set Reset SetHold
S
R
Q
Q
Hold10
10
10
10
Also called:R-S Latch
Set-Reset FF
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Clocked R-S Flip Flop• Logic Symbol Wiring Diagram
• Truth Table Waveform DiagramMode ofOperati
on
InputCLK
InputS
InputR
OutputQ
OutputQ
Effect
Hold 0 0 1 1 NoChange
Reset 0 1 0 1 Reset or cleared
to 0
Set 1 0 1 0 Set to 1
Prohibited1 1 1 1 Do not
use
Input
Output
S
R
Q
Q
10
10
10
10
Set
Reset Complementary
NormalInput Output
ClockS
R
Q
Q
FF
CLK
CLK
Output FF operates Synchronously
in step with clock.
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Questions• Q. What type of waveform is used in flip flops?
• A. Square Waves.
• Q. What does the RS stand for in the RS Flip Flop?
• A. Reset Set.
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D Flip Flop• Logic Symbol Wiring Diagram
Data
Clock Complementary
NormalD
CLK
Q
Q
FF
• Truth Table Similar Wiring
Input Output
Also called:Delay FFData FF
D-type Latches‘Delayed 1
Clock Pulse’
Input
CLKInput
DOutput
Qn+1
Output
Q
0 0 1
1 1 0
D
CLK
Q
Q
FF
S
R
Q
Q
FF
CLK =
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7474 D Flip Flop• Logic Symbol
• Truth Table
Data
Clock Complementary
NormalD
CLK
Q
Q
FFInput Output
Mode ofOperation
INPUTS OUTPUTSAsynchronous Synchronous
PS CLR CLK D Q Q
Asynchronous Set 0 1 X X 1 0
Asynchronous Reset 1 0 X X 0 1
Prohibited 0 0 X X 1 1
Set 1 1 L to H 1 1 0
Reset 1 1 L to H 0 0 1
Note: The asynchronous inputs(PS & CLR) Override the synchronous inputs (D & CLK) .
PS
Preset
ClearCLR
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D (Delay) Flip Flop Uses• Sequential logic devices used in temporary
memory devices.
• Wired together to form shift registers and storage registers.
• Delays data from reaching output Q one clock pulse.
• CMOS examples: 74HC74, 74FCT374, 40174
• Over 50 different ICs in FACT CMOS family.
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J-K Flip Flop• Logic Symbol
• Truth Table Mode of
OperationINPUTS OUTPUTS Effect
InputCLK
InputJ
InputK
OutputQ
OutputQ
Hold 0 0 NoChange
NoChange
NoChange
Reset 0 1 0 1 Reset or cleared to 0
Set 1 0 1 0 Set to 1
Toggle 1 1 Toggle Toggle Changed toOpposite State
Data
Complementary
NormalInput Output
ClockJ
K
Q
Q
FF
CLK
Data
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7476 J-K Flip Flop• Logic Symbol
• Truth Table Mode ofOperation
INPUTS OUTPUTSAsynchronous Synchronous
PS CLR CLK J K Q Q
Asynchronous Set 0 1 X X X 1 0
Asynchronous Reset 1 0 X X X 0 1
Prohibited 0 0 X X X 1 1
Hold 1 1 0 0 No Change No Change
Reset 1 1 0 1 0 1
Set 1 1 1 0 1 0
Toggle 1 1 1 1 Opposite State
Note: 7476 uses the entire pulse totransfer data from J & K data inputsto Q & Q outputs.
Data
Complementary
NormalInput Output
ClockJ
K
Q
Q
FF
CLK
Data
Preset
ClearCLR
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J-K Flip Flop Uses• Universal Flip Flop. Has all features of other FF.
• When being used only in the toggle mode, commonly called a T Flip Flop.
• CMOS examples: 74HC76, 74AC109, 4027.
• Most commonly used as counters.
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Questions• Q. What circuit can be used to give a clock
signal?
• A. Astable multivibrater.
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IC LatchesInput
Keyboard
7 8 9
1
4 5 6
2 3
0
Encoder 4-Bit Latch Decoder
OutputDisplay
Decimal DecimalBinary
•A device that serves as a temporary buffer memory is called a latch. An example of a 4-bit latch is the 7475.•A latch is transparent when the enable input is high, the normal outputs follow the data in the D inputs.•One example of flip flops is to latch or hold data.
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IC Latch Uses• The latch is the fundamental memory device
used in digital electronics.
• Almost all digital equipment contains simple memory devices called latches.
• CMOS examples: 4042, 4099, 74HC75
• 4043 is an example of a BCD-7 Segment latch/decoder/driver chip.
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CMOS D Flip-Flop Schematic
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D Flip Flop using Nor gatesWhat logic gates are more efficient?
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CMOS D Flip-Flop • CMOS technology allows a very different
approach to flip-flop design and construction. Instead of using logic gates to connect the clock signal to the master and slave sections of the flip-flop, a CMOS flip-flop uses transmission gates to control the data connections.
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Triggering Flip Flops• The added inverter bubble at the clock input
shows that triggering occurs on the negative going edge of the clock pulse.
• The J-K master/slave flip flop uses the entire pulse (positive edge and the negative edge) to trigger the flip flop.
• Waveform 165.
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Schmidt Trigger• Schmidt Trigger Inverter commonly used to
square up input signal. This reshaping of the waveform is called signal conditioning.
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IEEE vs. Logical Symbols• See internet links.
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Conclusions• Q. What are some circuit uses for flip flops?
• A. Counters, shift registers, and various memory devices.
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