Arithmetic Functions and Circuits
Chapter 5
2Digital Circuits
Overview
Iterative combinational circuits Binary adders
Half and full adders Ripple carry and carry lookahead adders
Binary subtraction Binary adder-subtractors
Signed binary numbers Signed binary addition and subtraction Overflow
Binary multiplication Other arithmetic functions
Design by contraction
3Digital Circuits
Iterative Combinational Circuits
Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position
Can design functional block for subfunction and repeat to obtain functional block for overall function
Cell - subfunction block Iterative array - a array of interconnected cells An iterative array can be in a single dimension
(1D) or multiple dimensions
4Digital Circuits
Cell n-1Xn-1
Y n-1
A n-1Bn-1
Cn-1
Xn
Y nCell 1
X1
Y 1
A 1
C1
Cell 0X0
Y 0
B0
C0
X2
Y 2
Block Diagram of a 1D Iterative Array
Example: n = 32 Number of inputs = ? Truth table rows = ? Equations with up to ? input variables Equations with huge number of terms Design impractical!
Iterative array takes advantage of the regularity to make design feasible
5Digital Circuits
Functional Blocks: Addition
Binary addition used frequently Addition Development:
Half-Adder (HA), a 2-input bit-wise addition functional block,
Full-Adder (FA), a 3-input bit-wise addition functional block,
Ripple Carry Adder, an iterative array to perform binary addition, and
Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance.
6Digital Circuits
Functional Block: Half-Adder
A 2-input, 1-bit width binary adder that performs the following computations:
A half adder adds two bits to produce a two-bit sum The sum is expressed as a
sum bit , S and a carry bit, C The half adder can be specified
as a truth table for S and C
X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 0 0 1 0 1 1 0
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
7Digital Circuits
Logic Simplification: Half-Adder
The K-Map for S, C is: This is a pretty trivial map!
By inspection:
and
These equations lead to several implementations.
Y
X
0 1
321
1
S Y
X
0 1
32 1
C
)YX()YX(S
YXYXYXS
)(C
YXC
)YX(
8Digital Circuits
Five Implementations: Half-Adder
We can derive following sets of equations for a half-adder:
(a), (b), and (e) are SOP, POS, and XOR implementations for S.
In (c), the C function is used as a term in the AND-NOR implementation of S, and in (d), the function is used in a POS term for S.
YXC)(S)c(
YXC)YX()YX(S)b(
YXCYXYXS)a(
YXC
YXCYXS)e(
)YX(CC)YX(S)d(
C
9Digital Circuits
Implementations: Half-Adder The most common half
adder implementation is: (e)
A NAND only implementation is:
YXCYXS
)(CC)YX(S
)YX(
XY
C
S
X
Y
C
S
10Digital Circuits
Functional Block: Full-Adder
A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C.
For a carry-in (Z) of 0, it is the same as the half-adder:
For a carry- in(Z) of 1:
Z 0 0 0 0
X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 0 0 1 0 1 1 0
Z 1 1 1 1
X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 1 1 0 1 0 1 1
11Digital Circuits
Logic Optimization: Full-Adder Full-Adder Truth Table:
Full-Adder K-Map:
X Y Z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
X
Y
Z
0 1 3 2
4 5 7 61
1
1
1
S
X
Y
Z
0 1 3 2
4 5 7 61 11
1
C
12Digital Circuits
Equations: Full-Adder
From the K-Map, we get:
The S function is the three-bit XOR function (Odd Function):
The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if the sum is 1 and a carry-in (Z) occurs. Thus C can be re-written as:
The term X·Y is carry generate. The term XY is carry propagate.
ZYZXYXCZYXZYXZYXZYXS
ZYXS
Z)YX(YXC
13Digital Circuits
Implementation: Full Adder
Full Adder Schematic
Here X, Y, and Z, and C(from the previous pages)are A, B, Ci and Co,respectively. Also, G = generate and P = propagate.
Note: This is really a combinationof a 3-bit odd function (for S)) andCarry logic (for Co):
(G = Generate) OR (P =Propagate AND Ci = Carry In)
Co G + P · Ci
Ai Bi
Ci
Ci+1
Gi
Pi
Si
14Digital Circuits
Binary Adders
To add multiple operands, we “bundle” logical signals together into vectors and use functional blocks that operate on the vectors
Example: 4-bit ripple carryadder: Adds input vectors A(3:0) and B(3:0) to geta sum vector S(3:0)
Note: carry out of cell ibecomes carry in of celli + 1
Description Subscript 3 2 1 0
Name
Carry In 0 1 1 0 Ci
Augend 1 0 1 1 Ai
Addend 0 0 1 1 Bi
Sum 1 1 1 0 Si
Carry out
0 0 1 1 Ci+1
15Digital Circuits
4-bit Ripple-Carry Binary Adder
A four-bit Ripple Carry Adder made from four 1-bit Full Adders:
B3 A 3
FA
B2 A 2
FA
B1
S3C4
C0
C3 C2 C1
S2 S1 S0
A 1
FA
B0 A
16Digital Circuits
Carry Propagation & Delay
One problem with the addition of binary numbers is the length of time to propagate the ripple carry from the least significant bit to the most significant bit.
The gate-level propagation path for a 4-bit ripple carry adder of the last example:
Note: The "long path" is from A0 or B0 though the circuit to S3.
A3B3
S3
B2
S2
B1
S1 S0
B0
A2 A1 A0
C4
C3 C2 C1 C0
17Digital Circuits
Carry Lookahead
Given Stage i from a Full Adder, we know that there will be a carry generated when Ai = Bi = "1", whether or not there is a carry-in.
Alternately, there will be a carry propagated if the “half-sum” is "1" and acarry-in, Ci occurs.
These two signal conditions are called generate, denoted as Gi, and propagate, denoted as Pi respectively and are identified in the circuit:
Ai Bi
Ci
Ci+1
Gi
Pi
Si
18Digital Circuits
Carry Lookahead (continued)
In the ripple carry adder: Gi, Pi, and Si are local to each cell of the adder Ci is also local each cell
In the carry lookahead adder, in order to reduce the length of the carry chain, Ci is changed to a more global function spanning multiple cells
Defining the equations for the Full Adder in term of the Pi and Gi:
iiiiii BAGBAP
iii1iiii CPGCCPS
19Digital Circuits
Carry Lookahead Development
Ci+1 can be removed from the cells and used to derive a set of carry equations spanning multiple cells.
Beginning at the cell 0 with carry in C0:
C1 = G0 + P0 C0
C4 = G3 + P3 C3 = G3 + P3G2 + P3P2G1
+ P3P2P1G0 + P3P2P1P0 C0
C2 = G1 + P1 C1 = G1 + P1(G0 + P0 C0) = G1 + P1G0 + P1P0 C0
C3 = G2 + P2 C2 = G2 + P2(G1 + P1G0 + P1P0 C0) = G2 + P2G1 + P2P1G0 + P2P1P0 C0
20Digital Circuits
Logic diagram
21Digital Circuits
4-bit carry-look ahead adder propagation delay
22Digital Circuits
Group Carry Lookahead Logic Figure 5-6 in the text shows shows the implementation of
these equations for four bits. This could be extended to more than four bits; in practice, due to limited gate fan-in, such extension is not feasible.
Instead, the concept is extended another level by considering group generate (G0-3) and group propagate (P0-3) functions:
Using these two equations:
Thus, it is possible to have four 4-bit adders use one of the same carry lookahead circuit to speed up 16-bit addition
012330
0012312323330
PPPPP
GPPPPGPPGPGG
030304 CPGC
23Digital Circuits
Carry Lookahead Example
Specifications: 16-bit CLA Delays:
NOT = 1 XOR = Isolated AND = 3 AND-OR = 2
Longest Delays: Ripple carry adder* = 3 + 15 x 2 + 3 = 36 CLA = 3 + 3 x2 + 3 = 12
*See slide 16
CLA CLA CLA CLA
CLA
33
2
22
24Digital Circuits
Unsigned Subtraction
Algorithm: Subtract the subtrahend N from the minuend M If no end borrow occurs, then M N, and the
result is a non-negative number and correct. If an end borrow occurs, the N > M and the
difference M N + 2n is subtracted from 2n, and a minus sign is appended to the result.
Examples: 0 1 1001 0100 0111 0111 0010 1101 10000 1101 () 0011
25Digital Circuits
Unsigned Subtraction (continued) The subtraction, 2n N, is taking the 2’s
complement of N To do both unsigned addition and unsigned
subtraction requires: Quite complex! Goal: Shared simpler
logic for both additionand subtraction
Introduce complementsas an approach
A B
Binary adder Binary subtractor
Selective2's complementer
Quadruple 2-to-1multiplexer
Result
Borrow
Complement
S0 1Subtract/Add
26Digital Circuits
Complements
Two complements: Diminished Radix Complement of N
(r 1)’s complement for radix r 1’s complement for radix 2 Defined as (rn
Radix Complement r’s complement for radix r 2’s complement in binary Defined as rn N
Subtraction is done by adding the complement of the subtrahend
If the result is negative, takes its 2’s complement
27Digital Circuits
Binary 1's Complement
For r = 2, N = 011100112, n = 8 (8 digits):
(rn – 1) = 256 -1 = 25510 or 111111112
The 1's complement of 011100112 is then:11111111
– 0111001110001100
Since the 2n – 1 factor consists of all 1's and since 1 – 0 = 1 and 1 – 1 = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT).
28Digital Circuits
Binary 2's Complement
For r = 2, N = 011100112, n = 8 (8 digits), we have:
(rn ) = 25610 or 1000000002
The 2's complement of 01110011 is then: 100000000
– 01110011 10001101
Note the result is the 1's complement plus 1, a fact that can be used in designing hardware
29Digital Circuits
Alternate 2’s Complement Method
Given: an n-bit binary number, beginning at the least significant bit and proceeding upward: Copy all least significant 0’s Copy the first 1 Complement all bits thereafter.
2’s Complement Example:10010100
Copy underlined bits: 100
and complement bits to the left:01101100
30Digital Circuits
Subtraction with 2’s Complement For n-digit, unsigned numbers M and N, find M N in base 2:
Add the 2's complement of the subtrahend N to the minuend M: M + (2n N) = M N + 2n
If M N, the sum produces end carry rn which is discarded; from above, M N remains.
If M < N, the sum does not produce an end carry and, from above, is equal to 2n ( N M ), the 2's complement of ( N M ).
To obtain the result (N – M) , take the 2's complement of the sum and place a to its left.
31Digital Circuits
Unsigned 2’s Complement Subtraction Example 1
Find 010101002 – 010000112
01010100 01010100
– 01000011 + 10111101
00010001 The carry of 1 indicates that no correction of
the result is required.
1
2’s comp
32Digital Circuits
Unsigned 2’s Complement Subtraction Example 2
Find 010000112 – 010101002
01000011 01000011 – 01010100 + 10101100
11101111 00010001
The carry of 0 indicates that a correction of the result is required.
Result = – (00010001)
0
2’s comp2’s comp
33Digital Circuits
Subtraction with Diminished Radix Complement
For n-digit, unsigned numbers M and N, find M N in base 2:
Add the 1's complement of the subtrahend N to the minuend M: M + (2n 1 N) = M N + 2n 1
If M N, the result is excess by 2n 1. The end carry 2n when discarded removes 2n, leaving a result short by 1. To fix this shortage, whenever and end carry occurs, add 1 in the LSB position. This is called the end-around carry.
If M < N, the sum does not produce an end carry and, from above, is equal to 2n 1 ( N M ), the 1's complement of( N M ).
To obtain the result (N – M) , take the 1's complement of the sum and place a to its left.
34Digital Circuits
Unsigned 1’s Complement Subtraction - Example 1
Find 010101002 – 010000112
01010100 01010100
– 01000011 + 10111100
00010000
+1
00010001 The end-around carry occurs.
1
1’s comp
35Digital Circuits
Unsigned 1’s Complement Subtraction Example 2
Find 010000112 – 010101002
01000011 01000011 – 01010100 + 10101011
1110111000010001
The carry of 0 indicates that a correction of the result is required.
Result = – (00010001)
1’s comp
1’s comp
0
36Digital Circuits
Signed Integers
Positive numbers and zero can be represented by unsigned n-digit, radix r numbers. We need a representation for negative numbers.
To represent a sign (+ or –) we need exactly one more bit of information (1 binary digit gives 21 = 2 elements which is exactly what is needed).
Since computers use binary numbers, by convention, the most significant bit is interpreted as a sign bit:
s an–2 a2a1a0
where: s = 0 for Positive numbers
s = 1 for Negative numbersand ai = 0 or 1 represent the magnitude in some form.
37Digital Circuits
Signed Integer Representations
Signed-Magnitude – here the n – 1 digits are interpreted as a positive magnitude.Signed-Complement – here the digits are interpreted as the rest of the complement of the number. There are two possibilities here:
Signed 1's Complement Uses 1's Complement Arithmetic
Signed 2's Complement Uses 2's Complement Arithmetic
38Digital Circuits
Signed Integer Representation Example r =2, n=3
Number Sign -Mag. 1's Comp. 2's Comp. +3 011 011 011 +2 010 010 010 +1 001 001 001 +0 000 000 000 – 0 100 111 — – 1 101 110 111 – 2 110 101 110 – 3 111 100 101 – 4 — — 100
39Digital Circuits
Signed-Magnitude Arithmetic
If the parity of the three signs is 0:1. Add the magnitudes.2. Check for overflow (a carry out of the MSB) 3. The sign of the result is the same as the sign of the
first operand. If the parity of the three signs is 1:
1. Subtract the second magnitude from the first.2. If a borrow occurs:
take the two’s complement of result• and make the result sign the complement of the
sign of the first operand.3. Overflow will never occur.
40Digital Circuits
Example 1: 0010 + 0101
Example 2: 0010 + 1101
Example 3: 1010 0101
Sign-Magnitude Arithmetic Examples
41Digital Circuits
Signed-Complement Arithmetic Addition:
1. Add the numbers including the sign bits, discarding a carry out of the sign bits (2's Complement), or using an end-around carry (1's Complement).
2. If the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred.
3. The sign of the result is computed in step 1. Subtraction:
Form the complement of the number you are subtracting and follow the rules for addition.
42Digital Circuits
Example 1: 1101 + 0011
Example 2: 1101 0011
Signed 2’s Complement Examples
43Digital Circuits
Example 1: 1101 + 0011
Example 2: 1101 0011
Signed 1’s Complement Examples
44Digital Circuits
2’s Complement Adder/Subtractor
Subtraction can be done by addition of the 2's Complement.
1. Complement each bit (1's Complement.)
2. Add 1 to the result. The circuit shown computes A + B and A – B: For S = 1, subtract,
the 2’s complementof B is formed by usingXORs to form the 1’scomp and adding the 1applied to C0.
For S = 0, add, B ispassed throughunchanged
FA FA FA FA
S
B3
C3
S2 S1 S0S3C4
C2 C1 C0
A 3 B2 A 2 B1 A 1 B0 A 0
45Digital Circuits
Overflow Detection
Overflow occurs if n + 1 bits are required to contain the result from an n-bit addition or subtraction
Overflow can occur for: Addition of two operands with the same sign Subtraction of operands with different signs
Signed number overflow cases with correct result sign 0 0 1 11 + 0 1 0 + 1 0 0 1 1
Detection can be performed by examining the result signs which should match the signs of the top operand
46Digital Circuits
Overflow Detection
Signed number cases with carries Cn and Cnshown for correct
result signs: 0 0 0 0 1 1 1 1
0 0 1 11 + 0 1 0 + 1 0 0 1 1
Signed number cases with carries shown for erroneous result signs (indicating overflow): 0 1 0 1 1 0 1 0
0 0 1 11 + 0 1 0 + 1 1 1 0 0
Simplest way to implement overflow V = Cn + Cn
This works correctly only if 1’s complement and the addition of the carry in of 1 is used to implement the complementation! Otherwise fails for 10 ... 0
47Digital Circuits
Binary Multiplication
The binary digit multiplication table is trivial:
This is simply the Boolean AND function.
Form larger products the same way we form larger products in base 10.
(a × b) b = 0 b = 1
a = 0 0 0
a = 1 0 1
48Digital Circuits
Review - Decimal Example: (237 × 149)10
Partial products are: 237 × 9, 237 × 4, and 237 × 1
Note that the partial product summation for n digit, base 10 numbers requires adding up to n digits (with carries).
Note also n × m digit multiply generates up to an m + n digit result.
2 3 7
× 1 4 9
2 1 3 3
9 4 8 -
+ 2 3 7 - -
3 5 3 1 3
49Digital Circuits
Binary Multiplication Algorithm
We execute radix 2 multiplication by: Computing partial products, and Justifying and summing the partial products. (same as
decimal) To compute partial products:
Multiply the row of multiplicand digits by each multiplier digit, one at a time.
With binary numbers, partial products are very simple! They are either:
all zero (if the multiplier digit is zero), or the same as the multiplicand (if the multiplier digit is one).
Note: No carries are added in partial product formation!
50Digital Circuits
Example: (101 x 011) Base 2
Partial products are: 101 × 1, 101 × 1, and 101 × 0
Note that the partial productsummation for n digit, base 2numbers requires adding upto n digits (with carries) ina column.
Note also n × m digit multiply generates up to an m + n digit result (same as decimal).
1 0 1
× 0 1 1
1 0 1
1 0 1
0 0 0
0 0 1 1 1 1
51Digital Circuits
Multiplier Boolean Equations
We can also make an n × m “block” multiplier and use that to form partial products.
Example: 2 × 2 – The logic equations for each partial-product binary digit are shown below:
We need to "add" the columns to getthe product bits P0, P1, P2, and P3.
Note that somecolumns maygenerate carries.
b1 b0
a1 a0
(a0 b1) (a0
b0)+ (a1
b1) (a1 b0)
P3 P2 P1 P0
52Digital Circuits
Multiplier Arrays Using Adders An implementation of the 2 × 2
multiplier array is shown:
C0C3
HA HA
C2 C1
A0
A1B1 B0
B1 B0
53Digital Circuits
Multiplier Using Wide Adders
A more “structured” way to develop an n × m multiplier is to sum partial products using adder trees
The partial products are formed using an n × m array of AND gates
Partial products are summed using m – 1 adders of width n bits
Example: 4-bit by 3-bit adder Text figure 5-11 shows a 4 × 3 = 12 element
array of AND gates and two 4-bit adders
54Digital Circuits
4-bit by 3-bit binary multiplier
55Digital Circuits
Cellular Multiplier Array
Another way to imple- ment multipliers is to usean n × m cellular array structure of uniform elements as shown:
Each element computes asingle bit product equalto ai·bj, and implementsa single bit full adder
Carry [ j, (k - 1)]
a[ j ]
b[ k ]
pp [ j , k ]
Cell [ j , k ]
Column Sum from above
Carry [ j , k ]
Column Sum to below
A BCo
SFACi
56Digital Circuits
Other Arithmetic Functions
Convenient to design the functional blocks by contraction - removal of redundancy from circuit to which input fixing has been applied
Functions Incrementing Decrementing Multiplication by Constant Division by Constant Zero Fill and Extension
57Digital Circuits
Design by Contraction
Contraction is a technique for simplifying the logic in a functional block to implement a different function
The new function must be realizable from the original function by applying rudimentary functions to its inputs
Contraction is treated here only for application of 0s and 1s (not for X and X)
After application of 0s and 1s, equations or the logic diagram are simplified by using rules given on pages 224 - 225 of the text.
58Digital Circuits
Design by Contraction Example
Contraction of a ripple carry adder to incrementer for n = 3 Set B = 001
The middle cell can be repeated to make an incrementer with n > 3.
A 2 A 1 A 0
S2 S1 S0
(b)
C3 5 XC0 5 0
S2
A 2X
X
0A 1 A 0
1
C1
54
3
1
2
00
S1
59Digital Circuits
Incrementing & Decrementing
Incrementing Adding a fixed value to an arithmetic variable Fixed value is often 1, called counting (up) Examples: A + 1, B + 4 Functional block is called incrementer
Decrementing Subtracting a fixed value from an arithmetic variable Fixed value is often 1, called counting (down) Examples: A 1, B 4 Functional block is called decrementer
60Digital Circuits
Multiplication/Division by 2n
(a) Multiplication by 100
Shift left by 2 (b) Division
by 100 Shift right by 2 Remainder
preserved
B0B1B2B3
C0C1
0 0
C2C3C4C5(a)
B0B1B2B3
C0 C21 C22C1C2
00
C3
(b)
61Digital Circuits
Multiplication by a Constant
Multiplication of B(3:0) by 101 See text Figure 513 (a) for contraction
B1B2B300 B 0B1B2B3
Carry
output
4-bit Adder
Sum
B0
C0C 1C2C3C4C5C6
62Digital Circuits
63Digital Circuits
Zero Fill
Zero fill - filling an m-bit operand with 0s to become an n-bit operand with n > m
Filling usually is applied to the MSB end of the operand, but can also be done on the LSB end
Example: 11110101 filled to 16 bits MSB end: 0000000011110101 LSB end: 1111010100000000
64Digital Circuits
Extension
Extension - increase in the number of bits at the MSB end of an operand by using a complement representation
Copies the MSB of the operand into the new positions
Positive operand example - 01110101 extended to 16 bits: 0000000001110101
Negative operand example - 11110101 extended to 16 bits: 1111111111110101
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