Workshop on Reliability and DfX Engineering for System-in ... Literatura...5) SAES getters - Viale...

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Workshop on Reliability and DfX Engineering for System-in-Package TechnologiesMay 29, 2008 Pallanza, Lago Maggiore, Italy

Reliability and Test Challenges around C2W and W2W SiP assemblies

N. Marenco 1, W. Reinert 1, S. Warnat 1, P. Lange 1,, , , g ,G. Allegato 2, T. Ungaretti 2, G. Hillmann 3, G. Bock 3,

W. Gal 4, S. Guadagnuolo 5, A. Conte 5, K. Friedel 6, K. Malecki 6, T. Falat 6

1) Fraunhofer Institute for Silicon Technology (ISIT) - Fraunhoferstrasse 1, 25524 Itzehoe, Germany2) ST Microelectronics - Via C. Olivetti 2, 20041 Agrate Brianza, Italy 3) Datacon Technology Innstrasse 16 6240 Radfeld Austria

Reliability and DfX Engineering for SiP TechnologiesPallanza (Italy) 29 May 2008


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3) Datacon Technology - Innstrasse 16, 6240 Radfeld, Austria4) FICO BV - Ratio 6, 6921 RW Duiven, The Netherlands5) SAES getters - Viale Italia 77, 20020 Lainate (MI), Italy 6) Wroclaw University of Technology - Wybrzeze Wyspianskiego 27, 50-370 Wroclaw, Poland

Today's MEMS packages for Automotive Inertial Measurement Units ("IMU")

Sensor Dynamics Gyroscope with



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y pfailsafe-logic (SD750)

open cavity plastic package SO24

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Market boost of IMUs: From automotive to consumer applications

Bosch-Sensortec Gyroscope (SMG040)PLCC 44 pin, ~12 x12 mm²

MEMS

Waferlevel-Package ASIC

PLCCPackage

3-axis accelerometer(SMB020 / SMB380)QFN and LGA available for consumer applications

3 x 3 x 0,9 mm³



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MEMS

www.bosch-sensortec.com

Low-cost MEMS Packagingin Consumer Applications

Stacked dies in QFN

Stacked dies in LGA



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STMicroelectronics e.g. 3-axis Accelerometer (LIS302) LGA 14 pin, 3 x 5 x 0,9 mm³

other LGA down to 3x3 mm²only a few products still in QFN28/44, 7x7x1,8mm³

STMicroelectronics

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CSP, WLP, SiP, ... Chip-Scale Package:Package size is determined by the die, not by the contact grid. Mostly small dies with low contact number:

High connectivity requires expensive board technologyIncreasing die size leads to larger CTE mismatch (use underfill)Smaller solder balls increase shear force

Wafer-Level Package:Packaging technology takes advantage of wafer-given batch processing. Main motivations are:

Stacking of geometrically matching dies to increase integration scaleEncapsulation of sensitive MEMS structures in clean environment Handling aspects for processing of thin wafers (e.g. via formation)



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System-in-Package:Smart subsystem of several components that appear as one:

Bypass interconnect technology gap (PCB vs. IC)Combine MEMS sensors or actuators with driver electronics

A "Chip-Scale System in a Waferlevel Package"

C2W-Integration:Direct MEMS-on-ASIC Bonding

MEMS-Sensors

Sealframe for Hermetic Encapsulation

Electrial Contacts: Processing and Bonding together with Sealframe



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CMOSCircuits(ASIC)

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W2W ok, but why C2W?

Wafer-to-Wafer (W2W)+ high throughput+ good process control

ASIC

- requires die & wafer matching- yield loss by mixing bad/good parts- extremely costly for lower volumes

Chip-to-Wafer (C2W)+ good design flexibility

MEMS

MEMS



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good design flexibility + suitable for low/medium volume+ multi-project realization possible- difficult MEMS handling ASIC

Waferlevel-Packaging - Today, Tomorrow

cap ASIC

IMU - ASIC

Multisensor-MEMSHigh-volume consumer applications

IMU = Inertial Measurement Unit

ASIC

MEMSMEMS

cap

Failsafe ASIC

MEMS

Failsafe ASIC

TSV

Solder BallsBackside

ContactsSealframeMEMS

DAVID project targets



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2008 2010 2012 2014

Multisensor-MEMS

Failsafe IMU - ASIC

Solder BallsBacksideRedistributionAutomotive and

other special markets

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Key Technologies for SiP – the DAVID Project

Inertial Sensor MEMS

ASIC

Waferlevel Molding

Face-to-Face contact MEMS/ASIC



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Through-Silicon Via

Solder-Balling

Redistribution Layer

Getter film

Vacuum Sealframe

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Vacuum technology

100 Nanoliters of almost nothing

98% Package0% Content

MEMS requirements:accelerometer 300...700 mbar

absol. pressure sensor 1...10 mbar

gyroscope, micromirror, ... 10-1 mbar



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gy p , ,bolometer < 10-4 mbar

RF switch < 10-4 mbar97% Content3% Package Automotive: Guaranteed for 15...17 years!

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Vacuum technology

Getter technology for WLPIn-cavity atmospheric conditions are defined by:

• wafer bonder chamber pressure• bondline quality: void- and leak free

tt fil it /• getter film capacity / area• getter activation profile• surface desorption• outgassing from device materials



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Getter on CMOS chips:New fine-structuring processGetter on CMOS chips:New fine-structuring process

Getter in passive caps:Shadow mask processGetter in passive caps:Shadow mask process

Vacuum technology

Vacuum Lifetime Prediction: Ultra-Fine Leak TestHow to ensure lifetime vacuum level before product delivery?Principle: Q-factor measurement of mechanical resonator1. Measure calibration curve (Q vs. p) of open resonator in vacuum chamber2 Determine 1st Q-factor wafer map of WLPs2. Determine 1 Q factor wafer map of WLPs3. Neon bombing (e.g. 24h at 3 bar)4. Determine 2nd Q-factor wafer map5. Calculate leak rate



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Resonator calibration curve Q vs. p

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Vacuum technology

Vacuum Lifetime Prediction: Ultra-Fine Leak Test

W. Reinert; D. Kahler; G. Longoni: "Assessment of vacuum lifetime in nL-packages"El t i P k i T h l C f 2005

Wafer map: Leak rate calculated after Ne bombing



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Electronic Packaging Technology Conference, 2005. EPTC 2005. Proceedings of 7th, vol.1, no., pp. 6 pp.-, 7-9 Dec. 2005

A. Conte; S. Guadagnuolo; A. Bonucci; W. Reinert; D. Kahler: “Improved lifetime prediction for vacuum encapsulated MEMS packages utilizing

getter technology and leak rate screening” Presentation at "Wafer bonding workshop" in Halle, Germany (Dec. 10, 2007)

Interconnect

The black box is not black, and it has no I/Os in it...

wire bondingC2W W2W

lateral feedthrough

Through-Silicon Via (TSV)



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solder balling

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Interconnect

Through-Silicon Via: Swiss Tunnels en miniature



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Von Mises – Stress: ~ 1 GPa at 400°C Risk of passivation cracking

due to thermomechanical loads(process or thermal ageing cycles)

Hermetic bonding

One by one or all at once?W2W::o) Fast throughput: Only batch processes involved:o\ Handling of two valuable, fully processed 8" wafers:o( Yield loss by combining bad devices with good ones!:o( Yield loss by combining bad devices with good ones!

TSV or contact window opening are mandatory (wafer thinning?) Thin wafer handling: Temperature conflict with temporary carrier bondingPreference not yet clear: Front-to-Front or Front-to-Back concept?

C2W::o( Risky handling (transport, particles):o) Advantage of yield control: Only good devices are combined!



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:o) Advantage of yield control: Only good devices are combined!:o\ Enhanced logistics for quality assurance and tracking

Necessitates wafer testing / mapping on MEMS (vacuum!) and on ASIC!Final test of SiP is equally necessary (+ calibration?)

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Hermetic bonding

Chip-to-Wafer Bonding ProcessStep 1: Pre-Fixation in die bonder

MEMSContactbumps Sealframe

US-bonding



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ASIC (wafer)Electroplated Interface Structures

Hermetic bonding

One by one: MEMS placement in a Die BonderAutomated die bonding generates particles !

Installation in a cleanroom cellUse of filtered air flowHandling concept and operator instructionHandling concept and operator instruction Basic machine constructionAvoid getter activation / saturation (ASIC on heated chuck)



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Datacon 2200apm

US-bonding prototype

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Hermetic bonding

"Clean-Running" the Die Bonder

filt

439

(<297)

119

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particles on wafer(dry run 0,5hrs)

Hepa Filte Fan

clean air flowfilterfanunit

Die-Bonder for ultrasonic prefixation

Class 1 000



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Class 1.000 environment

+Class 100

filter fan unit

Hermetic bonding

Chip offset and rotation error

T i l di b d / ff t 5 10



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Typical die-bonder x/y-offset: 5...10µmUltrasonic transducer amplitude ~2µm

Ultrasonic movement can cause chip rotationHow to recognize weak bonds due to only a slight rotation error? design measure

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Hermetic bonding

Chip-to-Wafer Bonding ProcessStep 2: Final Bonding in modified wafer bonder

Wafer bonder: Pressure plate

Vacuum VacuumMEMSContactbumps Sealframe



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ASIC (wafer)

Hermetic bonding

C2W: Final Bonding

Thermomechanical design leads to gap between chuck and wafer!

5000 N 6000 N



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High force destroys prefixation bump pads

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Hermetic bonding

C2W: Au-Sn Bonding Liquid formation is necessary for topography adaptation: Bonding at ~300°CInterdiffusion in Au-Sn eutectic formation: Risk of Ti plating base deterioration

Prefixation bump

Test pad matrix lateral offset



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p

Hermetic bonding

C2W: Au-Sn Bonding

Well-controlled temperature profile and distribution are mandatory! no Sn liquefaction

Sn shows aggressive diffusion into Au (Sn/Au ratio is to be reduced) Sealframe and contacts

interdiffusion starting at small contact points

Au/Al interdiffusion through Ti-Au plating base

Au should be thicker to



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Prefixation bumpsAu pad completely dissolved!

preserve plating base (Au/Al interdiffusion)

lateral geometry design to be defined

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Stealth laser dicing

It's magic: MEMS singulation with "Mahoh" dicingStealth dicing:

• Local melting of the silicon bulk material by a sharply focused laser beam (Hamamatsu photonics laser head)

Si melts

(Hamamatsu photonics laser head)

• Particle-free singulation by tape expansion

Dicing lanes must be free from any absorbing structuresNo polysilicon layer allowedRecommended scribeline width ~40% of wafer thickness



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E. Ohmura; F. Fukuyo; K. Fukumitsu; H. Morita: "Internal modified-layer formation mechanisms into silicon with nanosecond laser"Journal of Achievements in Materials and Manufacturing EngineeringJAMME 2006, vol.17, issue 1-2, pp. 381, 15 March 2006

22 scans / 690 µm wafer

Stealth laser dicing

Mahoh dicing with unoptimized MEMS design

Poly-SiPoly-Si transmission OK for bulk transforming.BUT: Insufficient weakening for singulation step!

Si (1,0,0) Bulk transformation to poly-Si



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Wafer Molding

"He needs must come along this hollow lane..." 1)

Transfer molding: Long-distance fill of narrow gap• 6" wafer mold under construction (8" targeted)• Working conditions: 130...170°C / 3...12 MPa• Specific material and process optimizations to avoid premature curingp p p p g• "Dynamic Temperature Control" 2) allows to minimize warpage



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1) 1805, "Wilhelm Tell", Friedrich Von Schiller

Cavity depth 880 umExposed MEMS and solderballs

Plunger 2) DTC is patented by FICO B.V.

Wafer Molding

Void formation during wafer molding

pad

3...12 MPa molding pressure:Critical load on TSV membrane!

TSV



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Risk of void formation(strong material dependence)

Tests tbd.1st trials with TSV filling

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Wafer Molding

Stress minimization in 6" wafer moldingCTE mismatch causes warpage!• Use of "Dynamic Temperature Control"

Mold cooling during cure time allows to reduce stress• Stress compensation by thickness-matched double-side molding

Si dummy chips

Design symmetry is limited by MEMS thickness and solder ball Ø• TSV filling demonstrated on 250 µm deep, 80 µm Ø blind holes

blind holes in Si dummy chips



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Exposure of solder balls TSV filling with mold compound

Conclusions

A technology zoo for MEMS-SiP integration...• Waferlevel encapsulation of MEMS progresses from "simple protection"

towards a highly functional combination of ASIC and MEMS.• In this context, W2W and C2W can address very complementary market

scenarios.• Structured deposition of thin-film getter allows optimal exploitation of the

available area. No interference with active CMOS device observed. • Lifetime reliability of vacuum packaged resonators can be assessed with

Neon bombing (ultra-fine leak detection).• Surprising new options appear as enabling factors for further advanced

packaging: Wafer molding, stealth laser dicing, thick-wafer TSV, ...• Lithography has to deal with backside alignment and vertical sidewalls

structures (spray coating equipment & materials); new failure potential!



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structures (spray coating equipment & materials); new failure potential!• 2nd level reliability of the presented packages… to be seen!

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“DAVID“ Downscaled Assembly of Vertically Interconnected Devices

Timeframe:1.1.2006 - 31.12.2008 IST-027240

STMicroelectronics Budget:5,3 M€2,8 M€ EU-Funding (FP6 STREP)

Scope:Hybrid MEMS Packaging

Application:



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www.david-project.eu

Inertial Measurement Unit

Workshop on Reliability and DfX Engineering for System-in ... Literatura...5) SAES getters - Viale...

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