Vlsi for Print

8/14/2019 Vlsi for Print

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Ex.NO:DESIGN AND SIMULATION OF COMPARATOR

Date:

AIM:

To design and simulate comparator using verilog program and schematic editor.

EQUIPMENTS AND SOFTWARE REQUIRED:

PC with Xilinx ISE 9.1

PC with Xilinx project navigator.

PROCEDURE:

A. VERILOG PROGRAM:1. Load Modelsim simulator.2. Open a new project and verilog programs for the given circuits in all the four

models of the project.

3. Simulate and verify the functionality of the circuit.

PROGRAM

module mag_comp(less,great,equal,a,b);

output less,great,equal;

input [3:0]a,b;

wire x1,x2,x3,x4,x5,x6,x7,x8;

wire y1,y2,y3,y4,y5,y6,y7,y8;wire z1,z2,z3,z4;

wire w1,w2,w3,w4,w5,w6;

not (x1,a[3]);

not (x2,b[3]);

not (x3,a[2]);

not (x4,b[2]);

not (x5,a[1]);

not (x6,b[1]);


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not (x7,a[0]);

not (x8,b[0]);

and(y1,x1,b[3]);and(y2,x2,a[3]);

and(y3,x3,b[2]);

and(y4,x4,a[2]);

and(y5,x5,b[1]);

and(y6,x6,a[1]);

and(y7,x7,b[0]);

and(y8,x8,a[0]);

nor(z1,y1,y2);

nor(z2,y3,y4);

nor(z3,y5,y6);nor(z4,y7,y8);

and(w1,z1,y3);

and(w2,z1,y4);

and(w3,z1,z2,y5);

and(w4,z1,z2,y6);

and(w5,z1,z2,z3,y8);

and(w6,z1,z2,z3,y8);

and(equal,z1,z2,z3,z4);

or(less,y1,w1,w3,w5);

or(great,y2,w2,w4,w6);

endmodule

OUTPUT


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B. SCHEMATIC EDITOR:1. Load Xilinx project navigator.2.

Create new project.

3. Create new source (schematic).4. Draw the given circuit diagram using schematic editor.5. View the RTL level schematic.6. Synthesis project and verify the results in modelsim.

CIRCUIT DIAGRAM


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OUTPUT

RESULT:

Thus the comparator circuits are designed using verilog and schematics and simulated

using modelsim simulator and Xilinx ISE.


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Ex.NO:DESIGN AND SIMULATION OF DECODER

Date:

AIM:

To design and simulate encoder using verilog program and schematic editor.




PROCEDURE:



3. Simulate and verify the functionality of the circuit.PROGRAM:

module decoder(d,a,b,e);

input a,b,e;

output [3:0] d;

wire abar,bbar,ebar;

not n1(abar,a);

not n2(bbar,b);not n3(ebar,e);

nand n4(d[0],abar,bbar,ebar);

nand n5(d[1],abar,b,ebar);

nand n6(d[2],a,bbar,ebar);

nand n7(d[3],a,b,ebar);

endmodule


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B. SCHEMATIC EDITOR:

1.

Load Xilinx project navigator.2. Create new project.3. Create new source (schematic).4. Draw the given circuit diagram using schematic editor.5. View the RTL level schematic.6. Synthesis project and verify the results in modelsim.

CIRCUIT DIAGRAM:

RESULT:

Thus the decoder circuits are designed using verilog and schematics and simulated using

modelsim simulator and Xilinx ISE.


7/16

Ex.NO:

DESIGN AND SIMULATION OF EQUALITY DETECTORDate:

AIM:

To design and simulate equality detector using verilog program and schematic editor.




PROCEDURE:

A.

VERILOG PROGRAM:1. Load Modelsim simulator.2. Open a new project and verilog programs for the given circuits in all the four


3. Simulate and verify the functionality of the circuit.PROGRAM

module equality_detect(equal,p,q,g);

output equal;

input [7:0]p,q;

input g;

wire [7:0]x;

wire[3:0]y;

wire w1,w2,w3,w4,w5;


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not(w1,g);

xnor(x[0],p[0],q[0]);

xnor(x[1],p[1],q[1]);

xnor(x[2],p[2],q[2]);

xnor(x[3],p[3],q[3]);

xnor(x[4],p[4],q[4]);

xnor(x[5],p[5],q[5]);

xnor(x[6],p[6],q[6]);

xnor(x[7],p[7],q[7]);

nand(y[0],x[0],x[1]);

nand(y[1],x[2],x[3]);

nand(y[2],x[4],x[5]);

nand(y[3],x[6],x[7]);

nor(w2,y[0],y[1]);

nor(w3,y[2],y[3]);

not(w5,w4);

noy(equal,w5);

endmodule

OUTPUT:


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B. SCHEMATIC EDITOR:1. Load Xilinx project navigator.2. Create new project.3. Create new source (schematic).4. Draw the given circuit diagram using schematic editor.5. View the RTL level schematic.6. Synthesis project and verify the results in modelsim.CIRCUIT DIAGRAM:


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OUTPUT:

RESULT:

Thus the equality detector circuits are designed using verilog and schematics and

simulated using modelsim simulator and Xilinx ISE.


11/16

Ex.NO:

DESIGN AND SIMULATION OF PRIORITY ENCODERDate:

AIM:

To design and simulate priority encoder using verilog program and schematic editor.




PROCEDURE:

A.

VERILOG PROGRAM:1. Load Modelsim simulator.2. Open a new project and verilog programs for the given circuits in all the four



module priority_encoder(encode0,encode1,valid,d0,d1,d2,d3);

output encode0,encode1,valid;

input d0,d1,d2,d3;

wire y1,y2;

not g1(y1,d2);

and g2(y2,y1,d1);

or g3(encode1,d3,y2);

or g4(encode0,d3,d2);

or g5(valid,encode0,d1,d0);

endmodule


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B. SCHEMATIC EDITOR:1. Load Xilinx project navigator.2. Create new project.3. Create new source (schematic).4. Draw the given circuit diagram using schematic editor.5. View the RTL level schematic.6. Synthesis project and verify the results in modelsim.

CIRCUIT DIAGRAM:

RESULT:

Thus the priority encoder circuits are designed using verilog and schematics and

simulated using modelsim simulator and Xilinx ISE.


13/16

Ex.NO:

DESIGN AND SIMULATION OF RIPPLE CARRY ADDERDate:

AIM:

To design and simulate ripple carry adder using verilog program and schematic editor.




PROCEDURE:




//gate level modeling for full adder //

module fa(cout,sum,a,b,cin);

output cout,sum;

input a,b,cin;

wire c1,c2,c3,s1;

xor g1(s1,a,b);

xor g2(sum,s1,cin);

and g3(c1,a,b);

and g4(c2,a,cin);

and g5(c3,b,cin);

or g6(cout,c1,c2,c3);

endmodule


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//gate level modeling for ripple carry adder//

module rca(cout,sum,a,b,cin);output cout;

output[3:0]sum;

input[3:0]a,b;

input cin;

wire[2:0]c;

fa(c[0],sum[0],a[0],b[0],cin);

fa(c[1],sum[1],a[1],b[1],c[0]);

fa(c[2],sum[2],a[2],b[2],c[1]);

fa(c[3],sum[3],a[3],b[3],c[2]);

endmodule

OUTPUT:


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B. SCHEMATIC EDITOR:1. Load Xilinx project navigator.2.

Create new project.

3. Create new source (schematic).4. Draw the given circuit diagram using schematic editor.5. View the RTL level schematic.6. Synthesis project and verify the results in modelsim.

CIRCUIT FOR FULL ADDER:

CIRCUIT FOR RIPPLE CARRY ADDER:


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OUTPUT

RESULT:

Thus the ripple carry adder circuits are designed using verilog and simulated using

modelsim simulator and Xilinx ISE.

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