VLSI Ppt for Calcutta University

8/13/2019 VLSI Ppt for Calcutta University

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Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Topics

Basic fabrication steps.

Transistor structures.

Basic transistor behavior.

Latch up.


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Fabrication services

Educational services:

U.S.: MOSIS

EC: EuroPractice

Taiwan: CIC

Japan: VDEC

Foundry = fabrication line for hire.

(A building equipped for the casting of metal orglass, microsoft office dictionary)

Foundries are major source of fab capacity today.


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Wafers

A waferis a thin slice of semiconducting material, such

as a silicon crystal, upon which microcircuits are

constructed by doping (for example, diffusion or ionimplantation, etching, and deposition of various materials.

Wafers are cut out of silicon boules A boule is a single crystal silicone from which

wafers are cut using diamond saws. http://en.wikipedia.org/wiki/Fabrication_%28semiconductor%29


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Fabrication Process

Once the wafers are prepared, many process steps are necessary to

produce the desired semiconductor integrated circuit. In general, the

steps can be grouped into four areas:

Front end processing (formation of transistors on silicon wafers) Back end processing (interconnection of transistors by metal wires)

Test

Packaging

In semiconductor device fabrication, the various processing steps fall into four

general categories: deposition, removal, patterning, and modification ofelectrical properties.

http://en.wikipedia.org/wiki/Fabrication_%28semiconductor%29


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Deposition

Deposition is any process that grows, coats, or otherwise transfers a material

onto the wafer. Available technologies consist of physical vapor deposition

(PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD),

molecular beam epitaxy (MBE) and more recently, atomic layer deposition

(ALD) among others.



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Removal or Etching Process

Removal processes are any that remove material from the wafer either

in bulk or selective form and consist primarily of etch processes, both

wet etching and dry etching such as reactive ion etch (RIE). Chemical

mechanical planarization (CMP) is also a removal process usedbetween levels.



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Masking and Patterning

Patterning covers the series of processes that shape or alter the existing shape

of the deposited materials and is generally referred to as lithography. For

example, in conventional lithography, the wafer is coated with a chemical

called a photoresist. The photoresist is exposed by a stepper, a machine that

focuses, aligns, and moves the mask, exposing select portions of the wafer toshort wavelength light. The unexposed regions are washed away by a

developer solution. After etching or other processing, the remaining

photoresist is removed by plasma ashing.

Many modern chips have eight or more levels produced in over 300 sequencedprocessing steps.



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Simple cross section

substraten+ n+

p+

substrate

metal1

poly

SiO2(insulator)

metal2

metal3

transistor via


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Photolithography

Mask patterns are put on wafer using photo-

sensitive material:

A typical wafer is made out of extremely pure silicon that isgrown into mono-crystalline cylindrical ingots (boules) up to 12

in (300 mm) in diameter using the Czochralski process. These

ingots are then sliced into wafers about 0.75 mm thick and

polished to obtain a very regular and flat surface.



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Process steps

First place tubs to provide properly-doped

substrate for n-type, p-type transistors:

(Front-end processing)

p-tub n-tub

substrate


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Process steps, contd.

Pattern polysilicon before diffusion regions:

p-tub p-tub

poly polygate oxide


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Process steps, contd

Add diffusions, performing self-masking:

p-tub p-tub

poly poly

n+n+ p+ p+


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Process steps, contd

Start adding metal layers: (Backend processing)

p-tub n-tub

poly poly

n+n+ p+ p+

metal 1 metal 1

vias


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Transistor structure

n-type transistor:


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0.25 micron transistor (Bell Labs)

poly

silicide

source/drain

gate oxide


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Transistor layout

n-type (tubs may vary):

w

L


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Electrical Transistor Model

Vgs: gate to source voltage

Vds: drain to source voltage

Ids: current flowing between drain andsource

k: transconductance > 0

Vt: threshold voltage > 0 for n-type


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Drain current characteristics


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Drain current

Linear region (Vds< Vgs- Vt):

Id= k (W/L)[(Vgs- Vt)Vds - 0.5Vds2]

Not quite a linear relation between Id

and Vds

but thequadratic term becomes more negligible than the linearterm as Vdsapproaches 0. This is typically the case withthe absolute value of the threshold Vtvoltage remainingclose to 0.

Saturation region (Vds>= Vgs- Vt): Id= 0.5k (W/L)(Vgs- Vt)

2

Idremains constant over changes in Vds

Increases with transconductance, channel width, and

decreases with channel length.


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0.5 m transconductances

From a MOSIS process:

n-type:

kn = 73 A/V2

Vtn= 0.7 V

p-type:

kp = 21 A/V2

Vtp= -0.8 V

C h h i


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Current through a transistor

(At saturation)

Example:Using 0.5 m transconductance parameter of 73

A/V2, threshold voltage of 0.7 volts,and SCMOS rules

(http://www.mosis.com/Technical/Designrules/scmos/scmos-

main.html)

with W 3, L = 2 :

Saturation current at Vgs= 2V:

Id= 0.5k(W/L)(Vgs-Vt)

2

= 93 A Saturation current at Vgs= 5V:

Id= 1012 A ~1 mA


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Basic transistor parasitics

There are myriad parasitics and parasitics models. The ones considered

here are the most widely-encountered parasitics.

Gate to substrate, also gate to source/drain.

Source/drain capacitance, resistance.

Cg

substrate


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Basic transistor parasitics, contd

Gate capacitance Cg. Determined by activearea.

Source/drain overlap capacitances Cgs, Cgd.Determined by source/gate and drain/gateoverlaps. Independent of transistor L.

Cgs= ColW (Colis the unit overlap capacitanceper m2, For small channel length, Col mightindirectly depend on L.)

Gate/bulk overlap capacitance.


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Latch-up

CMOS ICs have built-in undesirable parasitic

silicon-controlled rectifiers (SCRs).

When powered up, SCRs can turn on, creatinglow-resistance path from power to ground.

Current can destroy chip.

Early CMOS problem. Can be solved withproper circuit/layout structures.


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Silicon Controlled Rectifier(SCR)

Tyristor Circuit

In normal mode, no current flows over the pnpn path when the middlepn junction is reverse-biased. With the help of a gate pulse voltage,this pn junction can be forced into its breakdown region, making itconduct current. At that point, there will be a path of current from theanode to the cathode with no resistance even after the gate voltage iswithdrawn. This is the basis for a high current from VDD to theground (substrate) in MOS transistors, called the latch up.

QuickTime and a

TIFF (Uncompressed) decompressor

are needed to see this picture.

http://en.wikipedia.org/wiki/Thyristor

p

p

n

n

anode

cathode

gate

FB

FB

RB


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Parasitic SCR

circuit I-V behavior

V Reverse voltagebreakdown

Rsand Rw control the bias

voltage on the green diodes

FB

Breakdown

FB


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Parasitic SCR structure

n

pp

n

n

p

Solution: connect the n-tub to the VDD

When transistor on the right conducts, it turns on the

transistor on the left, and this in turn forces the first

transistor to draw more current, establishing a positive

feedback loop.


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Solution to latch-up

Use tub ties to connect tub to power rail. Use

enough to create low-voltage connection.

Doping the tub at the

point of contact reduces

the resistance of contact,and this makes it more

difficult for bipolar

transistor to turn on.


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Modern VLSI Design 3e: Chapter 2 Copyright 1998 2002 Prentice Hall PTR

Tub tie layout

metal (VDD)

n-tub

n+

You can learn more about latch up by downloading the article athttp://www.fairchildsemi.com/an/AN/AN-339.pdf#search=%22latch%20up%20problem%22

VLSI Ppt for Calcutta University

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