VLSI Design for Manufacturability
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Transcript of VLSI Design for Manufacturability
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VLSI Design for
Manufacturability
Keh-Jeng Chang
Department of Computer Science
National Tsing Hua UniversityMarch 12, 2004
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Outline
The VLSI Trend
Understanding DFM
Nanometer technology challenges
From technology to design: SIPPs
Nanometer design challenges
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The VLSI Trend
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VLSI CMOS BULK
* SEM picture courtesy of TSMC, Hsin-Chu, Taiwan
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State-of-the-Art CMOS
Sub-130nm CMOS transistors
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The Back-End of the Line
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Deep Submicron to Nanometer
1997 0.25um (8M random logic gates + RAM)
1999 0.18um (14M random logic gates + RAM)
2002 0.13um (24M random logic gates + RAM)
2005 90nm (40M random logic gates + RAM)
2008 65nm (64M random logic gates + RAM) 2011 45nm (100M random logic gates + RAM)
* Source http://www.itrs.org
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VLSI Design Flow
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VLSI Design+DFM Flow (1/2) Point tools and integrated tools are used.
RTL analysis
Floorplanning
Power analysis
Synthesis
Placement
STA
Routing
Physical
Synthesis
Virtual
Prototyping
RTL
DEF
V SI D i DFM Fl (2/2)
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VLSI Design+DFM Flow (2/2)
STA
Layout DRC
Noise check
EM check
ECO
Concurrent timing
& signal integrity:
+ reliability
+ manufacturability analysis+ optimization
DEF
DEF
Extraction
Delay calculation
DEF
DEF
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The Minimum Academia Can Do
Characterizing VLSI Performance
HSPICE
accurateBEOL
modeling
using
Raphael
accurateFEOL
modeling
using
BSIMPro
Characterizing Nanometer CMOS Technologies
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Legacy DFM (1/2)
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Legacy DFM (2/2)
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VLSI DFM Needs
How to survive:
Latchup
ESD
Substrate noise
Antenna effect Electromigration
Hot electron effect CMP dishing
Dummy metal STI and dummy diffusion
Slotted metal
OPC Shallow Trench Isolation
Process drifting and variation
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VLSI Yields Decrease @ 130nm
When the manufacturing foundries did everything
correctly, these five factors still affect yields:
Defects
Logic or analog design errors
Chips contain incorrect logic functions or analog functions
Process parameter variations
Incorrect or insufficient electrical characterization of the chipdesigns before manufacturing
Reliability
Insufficient electrical, material, or thermal characterization of thechip designs before manufacturing such as ESD, EM, et al.
Incorrect chip-package interface models
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Understanding DFM (1/2)
When transistors do not have the designed size;
When interconnect does not have the
anticipated R,L,C ; When the supplied voltage drops below 0.9*Vdd,
dynamically or statically;
When the coupling noise causes functional
errors at high slew rates;
When the guardband must be made morerealistic but cannot be more pessimistic.
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Understanding DFM (2/2)
Parametric yield
The circuit may work but the performance
such as speed, power consumption, gain,
and oscillation are subject to process
parameter uncertainties or variations. Defect limited yield
ESD, electromigration, antenna, particle,contamination,
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Nanometer Technology Challenges
Copper replacing aluminum
Low-K replacing silicon dioxide
Lower power supplies
Sub-wavelength lithography
Multiple-Vt CMOS
Tighter interconnect densities
Integrating digital+AMS+memory as SoC
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Copper Process Variations
Random variationsWithin-die and die-to-die variations
Critical Dimension (CD)
Sheet RhoMetal thickness
Low-K thickness and permittivity
Systematic variationsDensity-induced variations
Trapezoidal cross-section shapes
Dummy metals and diffusions [a.k.a. DFM]Metal slotting and cheesing [a.k.a. DFM]
Sub-wavelength OPC lithography [a.k.a. DFM]
Tall stack vias
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CMP-induced Variations
Cross-section of a pre-production 130-nm copper process
M7 final thickness: 0.447um (Target ~0.375um)
M6 final thickness: 0.375um (Target ~0.375um)
M5 final thickness: 0.414um (Target ~0.375um)
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Nanometer Design Challenges
Significant process variations
OPC/PSM
Signal integrity
Shortened time to market
Larger integration level with hierarchy
Faster slew rates
Lower power consumption budgets
Accurate BEOL Modeling
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h
hh11
hh22
s w
ss11
ss22
ww11
ww 22
tt1
tt22
t3w 3
a
b
p
1
2
3
Poly
M1
M2
M3
b
a
s3
pp pp pp
ttpp
Accurate BEOL Modeling Standard Interconnect
Performance Parameters (SIPPs):
1. critical dimensions (CD)
2. metal thickness
3. dielectric thickness
4. sheet R
5. via resistance
6. same-layer dielectric constant
7. inter-layer dielectric constant
Create Library of 3D primitivesCreate Library of 3D primitives (90,000 RC and 60,000 Ls per 1P8M process)
LibraryLibrary
Builder Pre-CharacterizedIPL LibraryBuilder
RC and L Field Solvers
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Noisy Neighbors
Delay uncertainty
Glitches on silent lines
==>D Q
D Q
Opp direction switching
9 Slows down the victim
9 Creates setup issues
Same direction switching
9 Speeds up the victim
9 Creates hold issues
C li I d d D l
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Coupling Induced Delay
Opposite direction switching: 1 m ~3Same direction switching: ~ -1 m 1
Cc Cc
m1Cc
m2Cc
m3Cc m4Cc
Simultaneous switching on coupled nets affects loading
Static timing analysis is done with grounded caps
m-factor is dependent on
9switching direction
9victim & aggressor edge times
9victim & aggressor drivers sizes
Hi hi l D i Ch ll
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Hierarchical Design Challenges
Block-levelAnalysis
Top-level routes:
Routing over
blocks
Hierarchical Parasitics,
Extraction
Top-level Analysis
memory
on-chip bus
Abstract model Abstract modelTiming, SI, abstraction for
blocks, macros, IP
M d li V lt D
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Ccell
Cp-well
BUFX1
Cn-well
DECAP1
Cdecap
Rdecap
Rdecap
Csignal
Ron
Ron
Rsignal
Resistive
Component
Capacitive
Component
Inductive
Component
V(t) = I(t).R + C.dv/dt.R + L.di/dt
Rpkg
Lpkg
Cpkg
Rpkg
Lpkg
Cpkg
On-chip
RVdd
CVdd
Vdd
Vss
CVss
RVss
Modeling Voltage Drop
Package +
bond-wire
On the Horizon
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On the Horizon
Design closure with third-party IPs
Packaging models
Interconnect inductance models
Spiral inductor models
Accurate leakage and powercharacterization
Designing matched components for analog
Substrate noise modeling and avoidance