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Background Statement for SEMI Draft Document #5450AREVISION TO SEMI M49-0912, GUIDE FOR SPECIFYING GEOMETRY MEASUREMENT SYSTEMS FOR SILICON WAFERS FOR THE 130 NM TO 22 NM TECHNOLOGY GENERATIONS WITH TITLE CHANGE TO: GUIDE FOR SPECIFYING GEOMETRY MEASUREMENT SYSTEMS FOR SILICON WAFERS FOR THE 130 NM TO 16 NM TECHNOLOGY GENERATIONS Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this Document.

Notice: Recipients of this Document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, “patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided.

BackgroundCurrent M49 documents is specifying upto 22nm technical generation, but recent technical discussion is being required next generation of 16nm generation technology which may start within several years together with 450mm wafer. This draft documents change following items. The corresponding original SNARF of line item revision was approved at Silicon Committee during SEMICON West July 2012 and revised as full ballot revision at Silicon Committee during Semicon Europe in Oct 2012The revision is adding ; Add Level3 Variability, Matching Tolerance and Bias for 16nm technology generation in Table 4 also add

16nm Scaling models in Table A1-2 Change 200mm usage for 32nm and 22nm Technical generation at Table 4.1.1 Change 450mm usage for 130nm, 90nm, 65nm and 45nm Technical generation at Table 3.1.3 and Table 4.1.3 Add SEMI M80 in 3.1 SEMI Standards and Table 1-1.7 Type of Cassettes as references. Clean up erroneous items and add information at Reference Wafer Properties in table 3, 4 and 5.

Review and Adjudication InformationTask Force Review Committee Adjudications

Group International AWG TF NA Silicon Wafer CommitteeDate April 1st 2013 April 2nd 2013Time & Time zone 13:30PM-17:00PM US Pacific Time 14:00PM-17:00PM US Pacific TimeLocation SEMI HQ SEMI HQCity, State/Country San Jose/California, US San Jose/California, USLeaders Masanori Yoshise ([email protected])

Satoshi Akiyama ([email protected])Dinesh Gupta ([email protected])Noel Poduje ([email protected])

Standard staff Kevin Nguyen ([email protected]) Kevin Nguyen ([email protected])

Note: Additions are indicated by underline and deletions are indicated by strikethrough.

mailto:[email protected]




DRAFTDocument Number: A

Date: 5/7/23

SEMI Draft Document #5450AREVISION TO SEMI M49-0912, GUIDE FOR SPECIFYING GEOMETRY MEASUREMENT SYSTEMS FOR SILICON WAFERS FOR THE 130 NM TO 22 NM TECHNOLOGY GENERATIONS WITH TITLE CHANGE TO: GUIDE FOR SPECIFYING GEOMETRY MEASUREMENT SYSTEMS FOR SILICON WAFERS FOR THE 130 NM TO 16 NM TECHNOLOGY GENERATIONS 1 Purpose1.1 This Guide provides recommendations for specifying measurement systems for geometry and flatness of silicon wafers of the 130, 90, 65, 45, 32, 22 and 1622 nm technology generation as anticipated by the International Technology Roadmap for Semiconductors (ITRS) and in the forecasts of the major manufacturers of semiconductor devices. Wafer parameters as defined by SEMI M1, SEMI M8, SEMI M11, SEMI M24, or SEMI M38 are specified by customers of silicon wafer suppliers and are usually part of Certificates of Compliance. Suppliers of silicon wafers and their customers might measure these parameters using equipment provided by different manufacturers of such equipment or using different generations of equipment of one supplier. Agreement on basic features and capability of such measurement systems improves data exchange and interpretation of data as well as procurement of appropriate measurement systems.

2 Scope2.1 This Guide outlines and recommends basic specifications for systems for measuring geometry and flatness of silicon wafers of the 130, 90, 65, 45, 32, 22 and 1622 nm technology generation.

2.2 This Guide applies to measurement systems used for verifying the quality parameters geometry and flatness in large scale production of bare polished or epitaxial silicon wafers the backside of which may be acid etched and/or covered by un-patterned, homogeneous layers of, for example, poly-Si or low temperature oxide (LTO). Artifacts (e.g., reference materials) for calibrating a measurement system might have different properties.

2.3 This Guide also applies to measurement systems that provide only a subset of the measurement features outlined in this Guide.

2.4 The Guide does not apply to measurement systems used to control intermediate process steps during Si wafer manufacturing. However, it may be completely or partly used for measurement systems for those applications provided corresponding constraints are appropriately identified.

2.5 The Guide also does not apply to measurement systems for SOI wafers or patterned wafers.

NOTICE: SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their use. It is the responsibility of the users of the Documents to establish appropriate safety and health practices, and determine the applicability of regulatory or other limitations prior to use.

3 Referenced Standards and Documents3.1 SEMI Standards and Safety Guidelines

SEMI E1.9 — Mechanical Specification for Cassettes Used to Transport and Store 300 mm Wafers

SEMI E5 — SEMI Equipment Communications Standard 2 Message Content (SECS-II)

SEMI E10 — Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) and Utilization

SEMI E19 — Standard Mechanical Interface (SMIF)

SEMI E30 — Generic Model for Communications and Control of Manufacturing Equipment (GEM)

SEMI E37 — High Speed SECS Message Services (HSMS) Generic Services

This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline. Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.

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Semiconductor Equipment and Materials International3081 Zanker RoadSan Jose, CA 95134-2127Phone: 408.943.6900, Fax: 408.943.7943


Date: 5/7/23

SEMI E47 — Specification for 150 mm/200 mm Pod Handles

SEMI E47.1 — Mechanical Specification for Boxes and Pods Used to Transport and Store 300 mm Wafers

SEMI E58 — Automated Reliability, Availability, and Maintainability Standard (ARAMS): Concepts, Behavior, and Services

SEMI E89 — Guide for Measurement System Analysis (MSA)

SEMI E158 — Mechanical Specification for Fab Wafer Carrier Used to Transport and Store 450 mm Wafers (450 FOUP) and Kinematic Coupling

SEMI E159 — Mechanical Specification for Multi Application Carrier (MAC) Used to Transport and Ship 450 mm Wafers

SEMI M1 — Specifications for Polished Single Crystal Silicon Wafers

SEMI M8 — Specification for Polished Monocrystalline Test Wafers

SEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers

SEMI M13 — Specification for Alphanumeric Marking of Silicon Wafers

SEMI M24 — Specification for Polished Monocrystalline Silicon Premium Wafers

SEMI M31 — Mechanical Specification for Front-Opening Shipping Box Used to Transport and Ship 300 mm Wafers

SEMI M38 — Specification for Polished Reclaimed Silicon Wafers

SEMI M43 — Guide for Reporting Wafer Nanotopography

SEMI M59 — Terminology for Silicon Technology

SEMI M62 — Specifications for Silicon Epitaxial Wafers

SEMI M67 — Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data Array Using the ESFQR, ESFQD and ESBIR Metrics

SEMI M68 — Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a Curvature Metric, ZDD

SEMI M73 — Test Methods for Extracting Relevant Characteristics from Measured Wafer Edge Profiles

SEMI M80 — MECHANICAL SPECIFICATION FOR FRONT-OPENING SHIPPING BOX USED TO TRANSPORT AND SHIP 450 mm WAFERS

SEMI MF42 — Test Methods for Conductivity Type of Extrinsic Semiconducting Materials

SEMI MF84 — Test Method for Measuring Resistivity of Silicon Wafers with an In-Line Four-Point Probe

SEMI MF534 — Test Method for Bow of Silicon Wafers

SEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Non-contact Scanning

SEMI MF671 — Test Method for Measuring Flat Length on Wafers of Silicon and Other Electronic Materials

SEMI MF673 — Test Methods for Measuring Resistivity of Semiconductor Wafers or Sheet Resistance of Semiconductor Films with a Noncontact Eddy-Current Gauge

SEMI MF928 — Test Methods for Edge Contour of Circular Semiconductor Wafers and Rigid Disk Substrates

SEMI MF1152 — Test Method for Dimensions of Notches on Silicon Wafers

SEMI MF1390 — Test Method for Measuring Warp on Silicon Wafers by Automated Non-Contact Scanning

SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Non-Contact Scanning


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SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Thickness Variation on Silicon Wafers by Automated Non-Contact Scanning

SEMI MF2074 — Guide for Measuring Diameter of Silicon and Other Semiconductor Wafers

SEMI T7 — Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol

3.2 DIN Standards1

DIN 50431 — Measurement of the Electrical Resistivity of Silicon or Germanium Single Crystals by Means of the Four-Point-Probe Direct Current Method with Collinear Probe Array

DIN 50432 — Determination of the Conductivity Type of Silicon or Germanium by Means of Rectification Test or Hot-Probe

DIN 50441-1 — Determination of the Geometric Dimensions of Semiconductor Slices; Measurement of Thickness

DIN 50441-2 — Determination of the Geometric Dimensions of Semiconductor Slices; Testing of Edge Rounding

DIN 50441-4 — Determination of the Geometric Dimensions of Semiconductor Slices; Diameter and Flat Depth of Slices

DIN 50441-5 — Determination of the Geometric Dimensions of Semiconductor Wafers; Terms of Shape and Flatness Deviation

DIN 50445 — Contactless Determination of the Electrical Resistivity of Semiconductor Wafers with the Eddy Current Method

3.3 IEEE Standards2

IEEE 754 — IEEE Standard for Binary Floating-Point Arithmetic

IEEE 802 — IEEE Standard for Local and Metropolitan Networks: Overview and Architecture

IEEE 854 — IEEE Standard Radix-Independent Floating-Point Arithmetic

3.4 ISO Standards3

ISO/IEC 8859 — Information Technology – 8-bit Single-Byte Coded Graphic Character Sets

ISO 8879 — Information Processing – Text and Office Systems – Standard Generalized Markup Language (SGML)

ISO 9000 — Quality Management Systems – Fundamentals and Vocabulary

ISO 9001 — Quality Management Systems – Requirements

ISO/IEC 10646-1 — Information Technology – Universal Multiple-octet Character Set (UCS) – Part 1: Architecture and Basic Multilingual Plane

ISO/IEC 10918 — Information Technology – Digital Compression and Coding of Continuous-Tone Still Images

ISO 14644-1 — Cleanroom and Associated Controlled Environments – Part 1: Classification of Air Cleanliness

3.5 JEITA Standards4

JEITA EM-3401 (43) — Terminology of Silicon Wafer Flatness

NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.

1 Deutsches Institut für Normung e.V., Available from Beuth Verlag GmbH, Burggrafenstrasse 4-10, D-10787 Berlin, Germany; http://www.din.de2 Institute of Electrical and Electronics Engineers, 3 Park Avenue, 17th Floor, New York, NY 10016-5997, USA; Telephone: 212.419.7900, Fax: 212.752.4929, http://www.ieee.org3 International Organization for Standardization, ISO Central Secretariat, 1 rue de Varembé, Case postale 56, CH-1211 Geneva 20, Switzerland; Telephone: 41.22.749.01.11, Fax: 41.22.733.34.30, http://www.iso.ch4 Japan Electronics and Information Technology Industries Association, Ote Center Building, 1-1-3, Otemachi, Chiyoda-ku, Tokyo 100-0004, Japan; http://www.jeita.or.jp


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4 Terminology4.1 General terms, acronyms, abbreviations and symbols associated with silicon technology and used in this Standard are listed and defined in SEMI M59.

5 Recommended Specification for Geometry Measurement Systems for Silicon Wafers5.1 The recommended specifications are structured in three sections (Tables 1 through 5):

Generic Equipment Characteristics (Table 1)

Materials to be measured (Table 2)

Metrology Specific Equipment Characteristics (Tables 3, 4 and 5)

5.2 Tables 1 through 5 contain the specifications, referenced documents, test methods, and comments. Additional explanations and discussions are provided in this section.

5.3 Generic Equipment Characteristics (Table 1)

5.3.1 The section “Generic Equipment Characteristics” consists of five subsections:

Wafer handling

Reliability

Procedural

Documentation

Computer/User Interface/Connectivity

5.3.2 Subsections covering ‘Facilities Requirements’ and ‘Safety/Legal/Regulatory’ are not included in the present document as these issues are highly user specific and dependent on national regulations.

5.4 Materials to be Measured (Table 2)

5.4.1 Table 2 specifies the parameters of silicon wafers that the measurement system must be capable to handle and to measure.

5.5 Metrology Specific Equipment Characteristics (Tables 3, 4 and 5)

5.5.1 This section specifies the dimensional parameters of silicon wafers to be measured and to be reported by systems for measuring the geometry and flatness of wafers as well as the required spatial resolution, precision and accuracy of the measurement system.

5.5.2 The ability of a measurement system to properly measure surface features of different spatial wavelengths is affected by the spatial bandwidth of the measurement system’s response function. Spatial bandwidth can be defined in many ways and is influenced by many factors beyond the scope of this Document. Some of these need to be standardized.

1: Some of these factors may need to be standardized. Additional information related to this topic can be found in: Mathematical Principles of Signal Processing, Pierre Brémaud, Springer, New York, 2002.

5.5.3 Spatial resolution is defined by the high spatial frequency limit of the bandwidth of the measurement system’s response function.

5.5.4 Low and high cut-off frequency fmin and fmax define the bandwidth of the response function of measurement systems. The cut-off frequencies correspond to an attenuation of 0.5 for the amplitude of a sinusoidal surface feature with the exception of a low pass filter (fmin = 0) for which the attenuation remains 1 at fmin.

5.5.5 The rate of change of the attenuation approaching the cut-off frequencies has to be larger than the rate of a Gaussian filter with the corresponding cut-off frequency.

5.5.6 This Guide recommends values of fmax and fmin that the measurement system must be capable of measuring.

5.5.7 Any variations in filtering procedures applied near the FQA boundary must be described by the supplier of the measurement system.


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5.5.8 The bandwidth as specified in Tables 3 and 4 is a nominal value.

5.5.9 This Guide uses a hierarchy of variability levels to describe the performance of a measurement system that is calibrated and adjusted/aligned according to the supplier’s procedures. The various terms are defined in SEMI M59.

5.5.9.1 Level 1 variability: standard deviation σ1



5.5.10 In addition two levels of systematic off-set between different measurement systems are defined:

5.5.10.1 Matching tolerance (difference of means Δm)

5.5.10.2 Correlation (regression curve)

5.5.11 Explicitly specified in the present document are only level 3 variability σ3 and matching tolerance Δm as they correspond to the utilization of measurement systems for wafer manufacturing most closely. The supplier of a specific measurement system may optionally provide specifications for level 1 and/or level 2 variability, respectively.

2: In the absence of certified or standard reference materials matching may be tested by using appropriate wafers complying with 130, 90, 65, 45, 32, 22 or 2216 nm technology node specifications, as appropriate. It is recommended to test for matching with a set of samples covering the parameter range of interest.

5.5.12 Level 3 variability σ3 and matching tolerance Δm are specified with respect to anticipated specifications for wafer geometry and flatness as given in Tables 3 and 4 for a reference wafer.

5.5.13 In the present document P/T-ratios (precision-to-tolerance ratios, see SEMI E89) are used for specifying level 3 variability σ3.

3: P/T-ratio is a metric for assessing the capability of metrology equipment for verifying a specimen (e.g. Si wafer) specification.

5.5.13.1 A P/T-ratio of 30% or less is recommended in SEMI E89 for metrology equipment. Geometry characteristics of Si wafers typically display either an approximately symmetric distribution around a median (a two-sided distribution), or a strongly skewed distribution with the median approaching zero, the lower specification boundary (a one-sided distribution). Therefore the P/T ratio is calculated either based on a 3 σ criterion for one-sided distributions or a 6 σ criterion for two-sided distributions and two grades are recommended for flatness and geometry measurement systems (see also R1):

Grade A: P/T < 10 %, 3 σ3 (one-sided distribution) or P/T < 10 %, 6 3 (two-sided distribution)

Grade B: P/T < 20 %, 3 σ3 (one-sided distribution) or P/T < 20 %, 6 3 (two-sided distribution)

5.5.13.2 The individual measurement features a measurement system provides may be graded differently (e.g., SFQR might meet grade A, but SBIR only grade B). This has to be indicated appropriately in the measurement systems’ technical specifications.

5.5.14 Matching tolerance is specified to be less or equal to 1.5 times level 3 variability (1.5 3). This corresponds to a greater than 99% probability that the difference of any individual measurement results obtained with two different measurement systems is smaller or equal to 5 σ3.

5.5.15 The target for bias is a range of ±1.5 σ3 with respect to a certified value provided that appropriate reference materials are available. This corresponds to a greater than 99% probability that any individual measurement is in the range of ±4 σ3 around the certified value when a reference material is tested.

5.5.16 Reference material with a series of surface features with appropriate height and half width is required to verify the bandwidth of a measurement system. The height of the features corresponds to the wafer specification as outlined in Tables 3 and 4.

5.5.17 All reference wafers shall meet the requirements listed in Tables 3, 4 and 5. Different wafers may be used to meet the flatness, nanotopography and edge profile requirements.

5.5.18 The specifications of a measurement system are verified by using reference wafers the parameters of which are in a range specified as follows:


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5.5.18.1 Thickness: nominal value ±20 µm.

5.5.18.2 Flatness, including near edge geometry, and shape: 0.5 to 1.5 times the nominal value. The nominal values are listed in Table 3 and Table 4 as Reference Wafer Specifications. For site related specifications not all sites must fall within the range, but the appropriate sites to be tested should be indicated. In all cases, at least three wafers in the range of values for each property shall be employed in the testing.

4: These nominal values also define the upper limit of the tolerance range for the flatness or shape characteristics with a lower limit or target value of zero.

5.5.18.3 Edge Profile — The ranges of the nominal values as listed in Table 5. The ITRS does not provide guidance regarding the specifications for edge profiles, therefore the ranges according to SEMI M73 are used for edge width and shoulder radius. The ranges for bevel angle and apex angle are based on common wafer specifications in semiconductor industry for current 300 mm wafers.

5: These ranges are also used as tolerances T for the edge profile characteristics, based on common practice in the semiconductor industry. The tolerances are also provided in Table 5 in the column “Comments and References”.

6: The edge region of wafers represents the most challenging area for meeting the desired performance characteristics. This is because of the larger surface geometry variations in the region near the edge (e.g., from polishing roll-off).

5.5.19 Verification of bias, matching tolerance and the various levels of variability are performed with a measurement system that has been calibrated according to the supplier’s procedures and that is under statistical process control. Procedures for determining level 1, 2, and 3 variability are given in § 6 and procedures for determining matching tolerance are given in § 7 .

5.5.20 Compatibility of two measurement systems is considered to be satisfactory when the specifications of the older measurement system are met with the newer measurement system operating in the emulation mode.

7: Compatibility can be provided by a measurement mode in which filtering, spatial resolution, etc. of another, older, measurement system is imitated.

5.5.21 The quality of a correlation between different measurement systems is not specified in this Guide.

6 Limited Reproducibility Tests8: Limited reproducibility tests such as those described in this section do not provide any indication of the various sources of variability or of their relative importance. If this type of information is desired, it is necessary to conduct a complete designed experiment with the appropriate analysis (see SEMI E89).

6.1 General

6.1.1 Select a single test wafer, typical of those to be measured by the measurement system (MS) being analyzed, for the test.

6.1.2 Select a number of measurements, n (where n ≥ 30, see Note 2), to be made on the same wafer.

9: The use of about 30 measurements has been found to generally provide low enough measurement uncertainty. If fewer measurements are used, the measurement uncertainty is increased, but the result is frequently satisfactory. The effect of sample size on uncertainty of the determination can be estimated by assuming that the measurement errors follow a normal distribution. Then, the uncertainty, expressed as a one-sided (upper) confidence interval, uci, around the estimate of repeatability is:

uci= σr√ n−1χn−1 ,α

2(1)

where:

σ r = estimate of repeatability from n measurements,

n = number of measurements made, and

χn−1, α2

= value that cuts off the upper fraction of a chi squared distribution with n 1 degrees of freedom.


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For example, if n = 15, the upper bound confidence interval is 1.46σ r . With n = 30, it is 1.28σ r , approximately a 12.5% reduction in uncertainty of the repeatability. If the n measurements are made on different measurands (e.g., on different sites on a wafer), the uncertainty is increased by a factor of [(n − 1) / (n − g)]1/2 where g is the number of groups, assumed to be of the same size.

6.1.3 Select the appropriate setup program for the measurements. The setup should be similar to that to be used by the MS in production or development, as appropriate.

6.1.4 Determine if the MS needs to be calibrated. Calibrate, if necessary, following the manufacturer’s recommended procedure. Do not recalibrate during the experiment unless required by the normal operating procedure.

6.2 Measurements — Perform the measurements appropriate to the level of variability to be determined.

6.2.1 Level 1 Variability — Load the test wafer in the MS and measure the property n times under repeatability conditions without unloading it from the instrument.

6.2.2 Level 2 Variability

6.2.2.1 Load the test wafer in the MS and measure the property once and then unload the wafer.

6.2.2.2 Reload the wafer into the MS and measure it once again in the shortest possible time, and then unload the wafer.

6.2.2.3 Repeat ¶ 6.2.2.2 (n – 2) more times in the shortest possible time interval so that a total of n measurements is made, unloading and reloading the wafer between each measurement, but otherwise under nominally identical conditions with a single calibration.

6.2.3 Level 3 Variability

6.2.3.1 Measure the test wafer for a total of n/D times per day under the conditions described in ¶ 6.2.2.1 through ¶ 6.2.2.3 on each of D days for a minimum of five days.

6.3 Calculations

6.3.1 Calculate the sample standard deviation of the test results:

s=√ 1(n−1) [∑k=1

n

(xk− x )2](2)

where:

s = sample standard deviation of the test results,

n = number of measurements made,

xk = kth test result, and

x = average value of the n test results.

6.3.2 The sample standard deviation is the unbiased estimator of the population standard deviation, . Therefore, take this sample standard deviation for the measurements in ¶ 6.2 as an estimate of the variability, r for the selected variability level.

7 Matching Tolerance Tests7.1 Determine the bias of each of two measurement systems of the same kind, using the procedures in § 8 of SEMI E89, under level 3 variability determination conditions.

7.2 If the results give a stable bias determination for each measurement system and if each system has acceptable linearity, subtract the two biases to obtain the matching tolerance, m.

Δm=bias1−bias2 (3)

where:


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bias1 = bias of the first measurement system and

bias2 = bias of the second measurement system.

8 Related Documents8.1 ASTM Standards5

ASTM E177 — Standard Practice for Use of the Terms Precision and Bias in ASTM Test Methods

ASTM E456 — Standard Terminology for Relating to Quality and Statistics

8.2 Other Documents

8.2.1 Evaluating Automated Wafer Measurement Instruments, SEMATECH6, Technology Transfer 94112638A-XFR

8.2.2 Metrology Tool Gauge Study Procedure for the International 300 mm Initiative (I300I), International 300 mm Initiative6, Technology Transfer #97063295A-XFR

8.2.3 International Technology Roadmap for Semiconductors: most recent edition6,7

8.2.4 ISO 3274-1996 — Geometrical Product Specifications (GPS) – Surface Texture: Profile method – Nominal characteristic of contact (stylus) instruments3

Table 1 Generic Equipment Characteristics

Item Recommended Specification Comment References

1 WAFER HANDLING1.1 Robot End Effector optional wafer edge or back surface contact edge as defined by

SEMI M11.2 Scan Stage optional wafer edge or back surface contact edge as defined by

SEMI M11.3 Wafer Contact Materials contact materials to leave metals and

organics on wafers < as defined in ITRS 991.4 Wafer Detection protection of accidental contact due to, for

example, cross-slotting double slotting, protrusions, etc.

1.5 Wafer Rotational Alignment random in, aligned out1.6 Number of Wafer Carrier Stations

2–4, arbitrary sender/receiver assignment

1.7 Type of Wafer Carriers open cassette, FOUP, SMIF pod, FOSB, MAC

to be specified alternatively

SEMI E1.9, SEMI E19, SEMI E47,

SEMI E47.1, SEMI M31,

SEMI E158 or SEMI E159,SEMI M80

1.8 Wafer Carrier Loading manual/guided vehicle, conveyor belt1.9 Automatic Wafer Carrier ID Reading

customer specific

1.10 Wafer Seating vertical or off-horizontal during setting wafer carrier on station by

operator

5 American Society for Testing and Materials, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959, USA; Telephone: 610.832.9585, Fax: 610.832.9555, http://www.astm.org6 SEMATECH, 257 Fuller Road, Suite 2200, Albany, NY 12203, USA; Telephone: 518.649.1000, http://www.sematech.org7 Recent versions of the ITRS are available from the homepage of International Sematech or ITRS: http:// www.sematech.org or http://www.itrs.net


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1.11 Wafer Carrier Filling Modes

random access and loading, programmable empty slot filling

1.12 Automatic Wafer ID Reading

customer specific

1.13 Particulate Contamination <0.001 PWP per cm2, >90 nm LSE front, and >120 nm LSE back surface#1

verify with mirror polished wafer

surfaces

SEMI E14

2 RELIABILITY2.1 MTBF >2000 h SEMI E102.2 MTTA >4 h SEMI E102.3 MTTR according to service contract SEMI E102.4 Availability >98% per year2.5 Uptime >160 h/w2.6 Response Time according to service contract2.7 Statistical Process Control (SPC) Performance

automated

2.8 Statistical Process Control (SPC) Machine Parameters

automated

3 PROCEDURAL3.1 Acceptance Testing customer specific3.2 Transport and Assembly customer specific3.3 Quality Assurance supplier conforming with ISO 9000/9001 ISO 9000/90013.4 Warranty >1 y3.5 Test Certificates customer specific3.6 Spares Availability >10 y3.7 Change Control supplier conforming with ISO 9000/9001 ISO 9000/90014 DOCUMENTATION4.1 Installation TBD4.2 Operation TBD4.3 Service TBD5 COMPUTER, USER INTERFACE, CONNECTIVITY5.1 Computer Operating System - Microsoft Windows NT 4.0 or higher, or

- Unix5.2 Display cleanroom compatible, class 4 ISO 14644-15.3 Keyboard cleanroom compatible, class 4 ISO 14644-15.4 Pointing Device cleanroom compatible, class 4 ISO 14644-15.5 Printer cleanroom compatible, class 4 ISO 14644-15.6 Data Processing - reprocessing of data

- parallel processing in different modes during measurement including sorting- multiprocessing (e.g., recipe editing, up/downloading during measurements)

different modes refer to data evaluation (e.g., for two different site patterns, or different emulation modes)

5.7 Data Access - access to basic measurement results (e.g., thickness map, height map)- data available at SECS/GEM/HSMS interface in real time

refers to all functions as defined in Tables 3 and 4

SEMI E5SEMI E30SEMI E37


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5.8 Data Analysis (Online/Offline)

on-line/off-line

5.9 Recipe Control - complete recipe generation off-line without machine specific data (calibration curves)- off-line recipe editing- remote recipe control by host computer- recipes are compatible between different software versions

5.10 Operating Sequence complete remote control : recipe download, start, stop, define data evaluation via SECS/GEM

SEMI E5

5.11 Data Interfaces - SECS/GEM- optional additionally a mass data standard transfer protocol (e.g., FTP#2)

SEMI E5

5.12 Material Tracking System Support

required, details user specific

5.13 Output File Format standardized formats:- ASCII or XML#3 for measurement results and optional for raw data- IEEE for raw data (floating point)- JPEG (or equivalent) for raw data (image data)

ISO/IEC 8859, ISO 8879

ISO/IEC 10646-1IEEE 754, IEEE 854

ISO/IEC 109185.14 Network Communications Standards Support

Ethernet, Fast Ethernet IEEE 802

5.15 SECS/GEM required SEMI E55.16 ARAMS required SEMI E58

#1 The particulate contamination PWP value given for the back surface has not been established in commercial practice and is under further consideration by the SEMI Silicon Wafer Committee.#2 Information about this protocol can be seen at the Web site of The World Wide Web Consortium at http:// www.w3.org/Protocols/rfc959 .#3 Information about XML can be found at http:// www.w3.org .

Table 2 Materials to be Measured

Item Recommended Specification Comments References

1 WAFERS1.1 Kind of Wafers monocrystalline, unpatterned

silicon wafers with layers as specified in Table 2, Item 1.3.4

SEMI M1(SEMI M8)

(SEMI M11)1.2 Wafer Characteristics – dimensional1.2.1 Wafer Diameter 200 or 300 or 450 or 200 and

300 and 450 mm nominalSEMI M1

SEMI MF2074DIN 50441-4

1.2.2 Wafer Thickness 200 mm wafers: 600–850 µm,300 mm wafers: 650–850 µm450 mm wafers: 800–1000 µm

See note #1,#2 SEMI MF1530 DIN 50441-1

1.2.3 Edge Shape rounded SEMI M1DIN 50441-2SEMI MF928

1.2.4 Wafer Shape Range 200 mm wafers: warp ≤100 µm,300 mm wafers: warp ≤200 µm450 mm wafers: warp ≤150 µm

SEMI M1SEMI MF1390 DIN 50441-5


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Item Recommended Specification Comments References

1.2.5 Fiducial 200 mm wafers: notch or flat300 and 450 mm wafers: notch

SEMI M1SEMI MF671 SEMI MF1152(DIN 50441-4)

1.2.6 ID Mark(s) 200 mm wafers: customer specific

300 and 450 mm wafers: according to SEMI Standards

content, type location of ID mark to be

specified

¶ 6.5.1 of SEMI M1

¶ 6.5.1.4 of SEMI M1

1.3 Wafer Characteristics – electrical, optical1.3.1 Electrical Resistivity of Wafers, Conductivity Type

0.5 m Ω·cm – intrinsic, p-, n-type Res: SEMI MF673DIN 50445

SEMI MF84DIN 50431

Type: SEMI MF42 or DIN 50432

1.3.2 Thermal Donors annealed and not annealed1.3.3 Wafer Charge no effect with respect to

measurement1.3.4 Layers (LTO, poly-Si), Epi LTO: thickness: 150–900 nm

uniformity: ≤10%poly-Si: thickness: ≤2 µm

uniformity: <20%Epitaxial layer: customer specific

1.3.5 Wafer Surface Conditions front surface: polished, annealed, or epitaxial layer

back surface: polished, acid and/or caustic etched, layers

according to Item 1.3.4

optional conditions of both surfaces: etched,

lapped, as cut

#1 Note that the thickness and shape ranges specified in Table 2 are intended to specify the full operating range of the equipment. This range is significantly wider than that of normal prime wafers and first reclaim wafers. Wafer parameter values for performance verification are specified in ¶ 5.5.17 and Tables 3 and 4. Performance of the measurement system as outlined in Tables 3 and 4 might be reduced for wafers with other thickness and shape values. The shape range given for 300 mm wafers, 200 μm, was established for measurement systems (e.g., capacitance-based) suitable for the 130 nm to 65 nm technology nodes. Systems (e.g., interferometer-based) with performance capability suitable for more advanced technology nodes (i.e., 45 nm and smaller) may have a reduced shape range (e.g., 100 μm) for 300 mm wafers.#2 Applications for other wafers (e.g., multiple reclaim, process development, special applications) may require other ranges which should be agreed upon between supplier and user.

Table 3 Metrology Specific Equipment Characteristics for 130, 90 and 65 nm Technology Generations

1. REFERENCE WAFER PROPERTIES (These wafer specifications refer only to wafers to be used for verifying the performance of a measurement system or systems, see ¶ 5.5.17. They do not refer to product wafers.)

Property130 nm Node 90 nm Node 65 nm Node

Nominal Nominal Nominal

1. REFERENCE WAFER PROPERTIES (These wafer specifications refer only to wafers to be used for verifying the performance of a measurement system or systems, see ¶ 5.5.17. and ¶ 5.5.18. They do not refer to product wafers.)1.1 Wafer thickness, m 1.1.1 Thickness (200 mm wafers), m 725 725 7251.1. 2 Thickness (300 mm wafers), m 775 775 7751.3. Thickness (450 mm wafers), µm 925 925 9251.42 GBIR, nm 1000 1000 10001.53 Site Size local flatness, mm2 25 × 25 26 × 8 26 × 8


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1.53.1 SBIR, including partial sites, nm 250 140 1251.53.2 SFQR, including partial sites, nm 130 60 451.64 Warp, m 30 30 30


Nominal Nominal Nominal1.75 Nanotopography, 2 mm, P-V, nm, at 0.05% defective area 20 16 10

1.86 Nanotopography, 10 mm, P-V, nm, at 0.05% defective area 70 50 35

Item Recommended Specification

Comments and ReferencesTechnology Generation 130 nm 90 nm#1 65 nm#1

Grade A B A B A B

2. MEASUREMENT FUNCTIONS2.1 Thickness (Center Point Thickness) SEMI M1,

SEMI MF15302.1.1 Level 3 Variability 3 (m, 1 ) ≤0.5 ≤1 ≤0.5 ≤1 ≤0.5 ≤12.1.2 Matching Tolerance m (m) ≤0.75 ≤1.5 ≤0.75 ≤1.5 ≤0.75 ≤1.52.1.3 Bias (m) ≤0.75 ≤1.5 ≤0.75 ≤1.5 ≤0.75 ≤1.5 Target until certified

reference materials are available

2.1.4 Spatial Bandwidthfmin (mm–1)fmax (mm–1)

01

Nominal value ±5% tolerance

2.2 Global Flatness (GBIR) SEMI M1 Appendix 1; SEMI MF1530; JEITA EM-3401 (43)

2.2.1 Level 3 Variability 3 (nm, 1 ) ≤30 ≤65 ≤30 ≤65 ≤30 ≤652.2.2 Matching Tolerance m (nm) ≤50 ≤100 ≤50 ≤100 ≤50 ≤1002.2.3 Bias (nm) ≤50 ≤100 ≤50 ≤100 ≤50 ≤100 Target until certified



01


2.3 Local Flatness (SBIR) SEMI M1 Appendix 1; SEMI MF1530; JEITA EM-3401 (43); DIN 50441-5

2.3.1 Level 3 Variability 3 (nm, 1 ) ≤8 ≤17 ≤4.7 ≤9.3 ≤4.2 ≤8.32.3.2 Matching Tolerance m (nm) ≤12 ≤26 ≤7 ≤14 ≤6.3 ≤12.52.3.3 Bias (nm) ≤12 ≤26 ≤7 ≤14 ≤6.3 ≤12.5 Target until certified



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Grade A B A B A B

2.4 Local Flatness (SFQR) Specifications apply on a site-by-site basis; SEMI M1 Appendix 1; SEMI MF1530; JEITA EM-3401 (43); DIN 50441-5

2.4.1 Level 3 Variability 3 (nm, 1 ) ≤4.5 ≤9 ≤2 ≤4 ≤1.5 ≤32.4.2 Matching Tolerance m (nm) ≤7 ≤13 ≤3 ≤6 ≤2.3 ≤4.52.4.3 Bias (nm) ≤7 ≤13 ≤3 ≤6 ≤2.3 ≤4.5 Target until certified



01


2.5 Shape (Warp, GMLYMER) SEMI M1 Appendix 2; SEMI MF1390; JEITA EM-3401 (43); DIN 50441-5

2.5.1 Level 3 Variability 3 (m, 1 ) ≤1 ≤2 ≤1 ≤2 ≤1 ≤22.5.2 Matching Tolerance m (m) ≤1.5 ≤3 ≤1.5 ≤3 ≤1.5 ≤32.5.3 Bias (m) ≤1.5 ≤3 ≤1.5 ≤3 ≤1.5 ≤32.5.4 Spatial Bandwidth

fmin (mm–1)fmax (mm–1)

01


2.6 Other Global Flatness Parameters SEMI M1 Appendix 1; SEMI MF1530; JEITA EM-3401 (43); DIN 50441-5

2.6.1 GFLR, GFLD required2.7 Other Local Flatness Parameters SEMI M1 Appendix 1;

SEMI MF1530; JEITA EM-3401 (43); DIN 50441-5

2.7.1 SBID, SFLR, SFLD, SFQD, SFSR, SFSD

required

2.8 Other Shape Parameters SEMI M1 Appendix 2; SEMI MF1390; JEITA EM-3401 (43); DIN 50441-5

2.8.1 Sori (GFLYFER), Bow (GM3YMCD), Warp (GB3NMPR)

required

2.9 Nanotopography These parameters refer to flatness measurement of individual surfaces; see SEMI M43.

2.9.1 Analysis Area Size = 2 mm2.9.1.1 Level 3 Variability 3 (nm, 1 ) ≤0.7 ≤1.3 ≤0.5 ≤1.1 ≤0.3 ≤0.72.9.1.2 Matching Tolerance m (nm) ≤1 ≤2 ≤0.8 ≤1.6 ≤0.5 ≤1


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Grade A B A B A B

2.9.1.3 Bias (nm) ≤1 ≤2 ≤0.8 ≤1.6 ≤0.5 ≤1 Target until certified reference materials are available

2.9.1.4 Spatial Bandwidthfmin (mm–1)fmax (mm–1)

0.052.5

Nominal value ±5% tolerance; optionally a range of fmin = 0.25 mm–1 to fmax = 2.5 mm–1

2.9.2 Analysis Area Size = 10 mm2.9.2.1 Level 3 Variability 3 (nm, 1 ) ≤2.5 ≤5 ≤1.7 ≤3.3 ≤1.2 ≤2.32.9.2.2 Matching Tolerance m (nm) ≤3.8 ≤7.5 ≤2.5 ≤5 ≤1.8 ≤3.52.9.2.3 Bias (nm) ≤3.8 ≤7.5 ≤2.5 ≤5 ≤1.8 ≤3.5 Target until certified



0.052.5

Nominal value ±5% tolerance; optionally a range of fmin = 0.05 mm–1 to fmax = 0.5 mm–1

2.10 Other Parameters2.10.1 Waviness customer specific2.10.2 Height (individual wafer surfaces)

customer specific

2.10.3 Slope customer specific2.10.4 Curvature customer specific2.10.5 Line Scans customer specific2.10.6 Contour Maps customer specific2.10.7 Data Histogram 10 or more bins per channel, arbitrarily definable,

cumulative differential2.10.8 Edge Roll-off customer specific2.10.9 Additional Parameters customer specific3. SETUP PARAMETERS3.1 Nominal Edge Exclusion defining FQA (mm)

≥2 ≥2 ≥1.5 Performance parameters are to be verified with nominal edge exclusion ≥2 mm. Instrument must be capable of reporting to nominal edge exclusion ≥1 mm. As a guide, the extended performance for nominal edge exclusion <2 mm should not exceed the performance (3, matching, bias) by more than 100% as compared to ≥2 mm edge exclusion given appropriate reference material.


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Grade A B A B A B

3.2 Site Patterns For local flatness: use any site pattern compatible with SEMI M1; for nanotopography use floating sites

Recommended range for site size: 5–40 mm, arbitrary combination of length of rectangular sides; see SEMI M1, SEMI M43

3.3 Sorting Criteria Sorting is performed by using logical ‘AND/OR’ combinations of multiple parameters

3.4 Exclusion Windows a) >3, curved or linear boundaries with arbitrary position anywhere on the entire wafer surfaceb) perimeter exclusion windows: N zones with total area covered ≤0.001 of total wafer area in the range R–2 mm to R, total perimeter excluded at R–1 mm ≤4% of total wafer circumference, no single zone longer than 5 mm.

a) For example, laser mark exclusion

4. PERFORMANCE4.1 Throughput4.1.1 200 mm Wafers >60 wafers per hour4.1.2 300 mm Wafers >40 wafers per hour4.1.3 450 mm Wafers >40 wafers per hour4.2 Downward Compatibility At least one previous measurement system generation of

supplierSpecific measurement systems involved need to be identified

4.3 Calibration Automated method, Certified Reference Material (CRM) to be provided by equipment supplier.

4.3.1 Level 3 Variability Test Interval ≥10 measurements over a period of not less than 2 weeks#2 To be performed with throughput mode used for qualifying product wafers, 95% confidence interval has to be less than the specified 3

4.4 Dependence of Results on Wafer Orientation

<1 3

#1 The values for variability, matching and bias for the 90 and 65 nm technology nodes are rounded to one significant decimal digit for those parameters which scale with the technology generations. Otherwise the values for the 130 nm generation are repeated.#2 This recommended specification is not intended to be a requirement for a two week pre-shipment test. Performance could be verified through routine statistical process control (SPC).

Table 4 Metrology Specific Equipment Characteristics for 45, 32, 22, and 2216 nm Technology Generations1. REFERENCE WAFER PROPERTIES (These wafer specifications refer only to wafers to be used for verifying the performance of the measurement equipment, see ¶ 5.5.17. They do not refer to product wafers.)

Property45 nm Node 32 nm Node 22 nm Node 16nm Node

Nominal Nominal Nominal Nominal

1. REFERENCE WAFER PROPERTIES (These wafer specifications refer only to wafers to be used for verifying the performance of the measurement system or systems, see ¶ 5.5.17. and ¶ 5.5.18 . They do not refer to product wafers.) 1.1 Wafer thickness, m


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1.1.1 Thickness (200 mm wafers#1), m 725 725N/A 725N/A N/A1.1. 2 Thickness (300 mm wafers), m 775 775 775 7751.1.3 Thickness (450 mm wafers#2), m 925N/A 925 925 9251.4 GBIR, nm 1000 1000 1000 1000


Nominal Nominal Nominal1.5 Site Size local flatness, mm2 26 × 8 26 × 8 26 × 8 26 ×81.5.1 SBIR, including partial sites, nm 110 101 95 911.5.2 SFQR, including partial sites, nm 30 21 15 111.6 Warp, m 30 30 30 301.7 Nanotopography, 2 mm, P-V, nm, at 0.05% defective area 7 5 4 3

1.8 Nanotopography, 10 mm, P-V, nm, at 0.05% defective area 25 17 12 8

1.9 ESFQR, nm72 sectors (θs = 5º), LR = 30 mm

125EE = 1 mm

88EE = 1 mm

64EE = 1 mm

43EE = 1 mm

1.10 ZDD, nm/mm2

16 sectors (θs = 22.5º)

−100at radius Rnom – 2

mm


mm


mmor


mm

-35at radius R nom – 2

mmor

-354at radius Rnom – 1

mm


Comments and ReferencesTechnology Generation 45 nm#3 32 nm#13 22 nm#13 16 nm #3

Grade A B A B A B A B

2. MEASUREMENT FUNCTIONS2.1.1 Thickness (Center Point Thickness) SEMI M1, SEMI

MF15302.1.1.1 Level 3 Variability 3 (m, 1 ) ≤0.5 ≤1 ≤0.5 ≤1 ≤0.5 ≤1 ≤0.5 ≤12.1.1.2 Matching Tolerance m (m) ≤0.75 ≤1.5 ≤0.75 ≤1.5 ≤0.75 ≤1.5 ≤0.75 ≤1.52.1.1.3 Bias (m) ≤0.75 ≤1.5 ≤0.75 ≤1.5 ≤0.75 ≤1.5 ≤0.75 ≤1.5 Target until certified

reference materials are available.


01


2.1.2 Global Flatness (GBIR) SEMI M1 Appendix 1; SEMI MF1530, JEIDA 43

2.1.2.1 Level 3 Variability 3 (nm, 1 ) ≤30 ≤65 ≤30 ≤65 ≤30 ≤65 ≤30 ≤652.1.2.2 Matching Tolerance m (nm) ≤50 ≤100 ≤50 ≤100 ≤50 ≤100 ≤50 ≤1002.1.2.3 Bias (nm) ≤50 ≤100 ≤50 ≤100 ≤50 ≤100 ≤50 ≤100 Target until certified



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2.1.3 Local Flatness (SBIR) SEMI M1 Appendix 1; SEMI MF1530; JEIDA 43; DIN 50441-5

2.1.3.1 Level 3 Variability 3 (nm, 1 ) ≤3.7 ≤7.4 ≤3.4 ≤6.8 ≤3.2 ≤6.4 ≤3.0 ≤6.02.1.3.2 Matching Tolerance m (nm) ≤5.5 ≤11 ≤5.1 ≤10.2 ≤4.8 ≤9.6 ≤4.5 ≤9.12.1.3.3 Bias (nm) ≤5.5 ≤11 ≤5.1 ≤10.2 ≤4.8 ≤9.6 ≤4.5 ≤9.1 Target until certified



01


2.1.4 Local Flatness (SFQR) Specifications apply on a site-by-site basis; SEMI M1 Appendix 1; SEMI MF1530; JEIDA 43; DIN 50441-5

2.1.4.1 Level 3 Variability 3 (nm, 1 ) ≤1 ≤2 ≤0.7 ≤1.4 ≤0.5 ≤1 ≤0.36 ≤0.712.1.4.2 Matching Tolerance m (nm) ≤1.5 ≤3 ≤1.1 ≤2.2 ≤0.8 ≤1.6 ≤0.53 ≤1.072.1.4.3 Bias (nm) ≤1.5 ≤3 ≤1.1 ≤2.2 ≤0.8 ≤1.6 ≤0.53 ≤1.07 Target until certified



01


2.1.5 Shape (Warp, GMLYMER) SEMI M1 Appendix 4; SEMI MF1390; JEIDA 43; DIN 50441-5

2.1.5.1 Level 3 Variability 3 (m, 1 ) ≤1 ≤2 ≤1 ≤2 ≤1 ≤2 ≤1 ≤22.1.5.2 Matching Tolerance m (m) ≤1.5 ≤3 ≤1.5 ≤3 ≤1.5 ≤3 ≤1.5 ≤32.1.5.3 Bias (m) ≤1.5 ≤3 ≤1.5 ≤3 ≤1.5 ≤3 ≤1.5 ≤32.1.5.4 Spatial Bandwidth

fmin (mm–1)fmax (mm–1)

01


2.1.6 Other Global Flatness Parameters SEMI M1 Appendix 1; SEMI MF1530; JEIDA 43; DIN 50441-5

2.1.6.1 GFLR, GFLD required2.1.7 Other Local Flatness Parameters SEMI M1 Appendix 1;

SEMI MF1530; JEIDA 43; DIN 50441-5

2.1.7.1 SBID, SFLR, SFLD, SFQD, SFSR, SFSD

required


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2.1.8 Other Shape Parameters SEMI M1 Appendix 4; SEMI MF1390; JEIDA 43; DIN 50441-5

2.1.8.1 Sori (GFLYFER), Bow (GM3YMCD), Warp (GB3NMPR)

required

2.2 Nanotopography These parameters refer to flatness measurement of individual surfaces; see SEMI M43.

2.2.1 Analysis Area Size = 2 mm2.2.1.1 Level 3 Variability 3 (nm, 1 ) ≤0.23 ≤0.4

6≤0.17 ≤0.34 ≤0.13 ≤0.26 ≤0.08 ≤0.17

2.2.1.2 Matching Tolerance m (nm) ≤0.35 ≤0.7 ≤0.25 ≤0.5 ≤0.2 ≤0.4 ≤0.13 ≤0.252.2.1.3 Bias (nm) ≤0.35 ≤0.7 ≤0.25 ≤0.5 ≤0.2 ≤0.4 ≤0.13 ≤0.25 Target until certified



0.052.5

Nominal value ±5% tolerance; optionally a range of fmin=0.25 mm–1 to fmax=2.5 mm–1

2.2.2 Analysis Area Size = 10 mm2.2.2.1 Level 3 Variability 3 (nm, 1 ) ≤0.83 ≤1.6

6≤0.57 ≤1.15 ≤0.4 ≤0.8 ≤0.28 ≤0.57

2.2.2.2 Matching Tolerance m (nm) ≤1.25 ≤2.5 ≤0.85 ≤1.7 ≤0.6 ≤1.2 ≤0.43 ≤0.852.2.2.3 Bias (nm) ≤1.25 ≤2.5 ≤0.85 ≤1.7 ≤0.6 ≤1.2 ≤0.43 ≤0.85 Target until certified



0.052.5

Nominal value ±5% tolerance; optionally a range of fmin=0.05 mm–1 to fmax=0.5 mm–1

2.3 Near-Edge Geometry (ERO)2.3.1 ESFQR SEMI M672.3.1.1 Level 3 Variability 3 (nm, 1 ) ≤4.2 ≤8.3 ≤2.9 ≤5.9 ≤2.1 ≤4.2 ≤1.4 ≤2.92.3.1.2 Matching Tolerance m (nm) ≤6.3 ≤12.

5≤4.4 ≤8.8 ≤3.1 ≤6.3 ≤2.2 ≤4.3

2.3.1.3 Bias (nm) ≤6.3 ≤12.5

≤4.4 ≤8.8 ≤3.1 ≤6.3 ≤2.2 ≤4.3 Target until certified reference materials are available.


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2.3.1.4 Data array point spacing ≤0.2 mm Data array point spacing in orthogonal directions on a Cartesian grid is specified instead of bandwidth for ERO parameters. This point spacing specification is reduced from that in SEMI M67 to enable these advanced technology generations.

2.3.2 ZDD at radius Rnom – 2 mm SEMI M682.3.2.1 Level 3 Variability 3 (nm/mm2, 1 )

≤3.3 ≤6.7 ≤2.4 ≤4.7 ≤1.7 ≤3.3 ≤1.2 ≤2.3

2.3.2.2 Matching Tolerance m (nm/mm2)

≤5.0 ≤10.0

≤3.5 ≤7.1 ≤2.5 ≤5.0 ≤1.7 ≤3.5

2.3.2.3 Bias (nm/mm2) ≤5.0 ≤10.0

≤3.5 ≤7.1 ≤2.5 ≤5.0 ≤1.7 ≤3.5 Target until certified reference materials are available.


2.3.3 ZDD at radius Rnom – 1 mm SEMI M682.3.3.1 Level 3 Variability 3 (nm/mm2, 1 )

≤16.7 ≤33.3 ≤11.8 ≤23.6

2.3.3.2 Matching Tolerance m (nm/mm2)

≤25.0 ≤50.0 ≤17.7 ≤35.4

2.3.3.3 Bias (nm/mm2) ≤25.0 ≤50.0 ≤17.7 ≤35.4 Target until certified reference materials are available.


2.3.4 Other ERO Parameters user specific2.4 Other Parameters2.4.1 Waviness user specific


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2.4.2 Height (individual wafer surfaces) user specific2.4.3 Slope user specific2.4.4 Curvature user specific2.4.5 Line Scans user specific2.4.6 Contour Maps user specific2.4.7 Data Histogram 10 or more bins per channel, arbitrarily definable,

cumulative differential2.4.8 Additional Parameters user specific3. SETUP PARAMETERS3.1 Nominal Edge Exclusiondefining FQA (mm)3.1.1 All Parameters except Near-Edge Geometry (ERO)

≥1.5 ≥1.5 ≥1.5 ≥1.5 Performance parameters are to be verified with nominal edge exclusion ≥2 mm. Instrument must be capable of reporting to nominal edge exclusion ≥1 mm. As a guide, the extended performance for nominal edge exclusion <2 mm should not exceed the performance (3, matching, bias) by more than 100% as compared to ≥2 mm edge exclusion given appropriate reference material.


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3.1.2 Near-Edge Geometry (ERO) Parameters (see note)3.1.2.1 ESFQR3.1.2.2 ZDD

≥1≥2

≥1≥2

≥1≥2 or ≥1

≥1≥2 or ≥1

For 1 mm Edge Exclusion for ZDD it is necessary to use an alternative calculation as described in § 9 Note 2 of SEMI M68.

Note: Although ITRS does not suggest using edge exclusions less than 2 mm for future generation device manufacturing, it is useful for starting materials edge geometry metrics to be evaluated using a 1 mm edge exclusion. These reduced edge exclusion metrics of edge roll-off provide sensitive indicators of starting material process capability when using a 2 mm edge exclusion during device manufacturing. Only ESFQR and ZDD metrics are specified at this reduced edge exclusion of 1 mm.

3.2 Site Patterns For local flatness: use any site pattern compatible with SEMI M1;

for nanotopography use floating sites.

Recommended range for site size: 5–40 mm, arbitrary combination of length of rectangular sides; see

SEMI M1, SEMI M43.3.3 Sorting Criteria Sorting is performed by using logical ‘AND/OR’

combinations of multiple parameters.3.4 Exclusion Windows a) >3, curved or linear boundaries with arbitrary position

anywhere on the entire wafer surfaceb) perimeter exclusion windows: N zones with total area

covered 0.001 of total wafer area in the range R – 2 mm to R, total perimeter excluded at R – 1 mm 4%

of total wafer circumference, no single zone longer than 5 mm.

a) e.g., laser mark exclusion

4. PERFORMANCE4.1 Throughput4.1.1 200 mm Wafers#1 >60 wafers

per hourN/A

4.1.2 300 mm Wafers >40 wafers per hour


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4.1.3 450 mm Wafers#2 >40 wafers per hour

N/A

>40 wafers per hour

4.2 Downward Compatibility At least one previous tool generation of supplier. Specific tools involved need to be identified.

4.3 Calibration Automated method, Certified Reference Material (CRM) to be provided by equipment supplier.

4.3.1 Level 3 Variability Test Interval ≥10 measurements over a period of not less than 2 weeks#2 To be performed with throughput mode used for qualifying product wafers, 95% confidence interval has to be less than the specified 3.

4.4 Dependence of Results on Wafer Orientation

<1 3

#1 200 mm diameter wafers are not included for 32nm and smaller node #2 450mm wafers are not included for 45nm and larger node. #3 The values for variability, matching and bias for the 45 to 2216 nm technology nodes are rounded to one two significant decimal digits for those parameters which scale with the technology generations. Otherwise the values for the 130 nm generation are repeated. #4 This recommended specification is not intended to be a requirement for a two week pre-shipment test. Performance could be verified through routine statistical process control (SPC).

Table 5 Metrology Specific Equipment Characteristics for Edge Profile Measurement#1

1. REFERENCE WAFER PROPERTIES (These wafer specifications refer only to wafers to be used for verifying the performance of the measurement equipment, see ¶ 5.5.17 and ¶ 5.5.18. They do not refer to product wafers.)

Property Nominal Range

1.1 Thickness (200 mm wafers), m 705–7451.2 Thickness (300 mm wafers), m 755–7951.3 Thickness (450 mm wafers), m 905–9451.4 Edge Profile #2, #3

1.4.1 Edge Width, front and back, µm 300–4001.4.2 Bevel Angle, front and back, ° 20.5–24.51.4.3 Shoulder Radius, front and back, µm 200–260

1.4.4 Apex Angle, front and back, ° 0–6

Item Recommended SpecificationComments and References

Grade A B

2. MEASUREMENT FUNCTIONS2.1 Edge Width SEMI M73

2.1.1 Level 3 Variability 3 (m, 1 ) ≤1.7 ≤3.4 T = 100 µm (±50 µm) in P/T, 6 (two-sided distribution)

2.1.2 Matching Tolerance m (m) ≤2.5 ≤5

2.1.3 Bias (m) ≤2.5 ≤5 Target until certified reference materials are available.

2.2 Bevel Angle (°) SEMI M73


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Item Recommended SpecificationComments and References

Grade A B

2.2.1 Level 3 Variability 3 (°, 1 ) ≤0.07 ≤0.14 T = 4° (± 2°) in P/T, 6 (two-sided distribution)

2.2.2 Matching Tolerance m (°) ≤0.1 ≤0.1

2.2.3 Bias (°) ≤0.1 ≤0.1 Target until certified reference materials are available.

2.3 Shoulder Radius (µm) SEMI M73

2.3.1 Level 3 Variability 3 (m, 1 ) ≤1 ≤2 T = 60 µm (± 30 µm) in P/T, 6 (two-sided distribution)



2.4 Apex Length (µm) SEMI M73

2.4.1 Level 3 Variability 3 (m, 1 ) ≤1 ≤2 T = 75 µm (±37.5 µm) in P/T, 6 (two-sided distribution)



2.5 Apex Angle (°) SEMI M73

2.5.1 Level 3 Variability 3 (°, 1 ) ≤0.2 ≤0.4 T = + 6° in P/T, 3 (one-sided distribution)

2.5.2 Matching Tolerance m (°) ≤0.3 ≤0.6

2.5.3 Bias (°) ≤0.3 ≤0.6 Target until certified reference materials are available.

3. SETUP PARAMETERS

3.1 Sorting CriteriaSorting is performed by using logical “AND/OR” combinations of multiple

parameters.3.2 Exclusion Windows none4. PERFORMANCE4.1 Throughput4.1.1 200 mm Wafers >60 wafers per hour4.1.2 300 mm Wafers >40 wafers per hour4.1.3 450 mm Wafers >40 wafers per hour

4.2 Downward Compatibility At least one previous tool generation of supplier.

Specific tools involved need to be identified.

4.3 CalibrationAutomated method, Certified Reference

Material (CRM) to be provided by equipment supplier.

4.3.1 Level 3 Variability Test Interval ≥10 measurements over a period of not less than 2 weeks#4

To be performed with throughput mode used for qualifying product wafers, 95% confidence interval has to be less than the specified 3.

4.4 Dependence of Results on Wafer Orientation <1 3

#1 No changes of edge profile specifications are expected over the various technology generations. Therefore this table applies to all technology generations for 200, 300 and 450 mm wafers.#2 Edge width and shoulder radius according to SEMI M73, edge profile A. Bevel angle and apex angle according to common wafer specifications in semiconductor industry.


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#3 The range for the apex length is not specified here. It can be calculated according to SEMI M73 based on wafer thickness, edge width, bevel angle and shoulder radius.#4 This recommended specification is not intended to be a requirement for a two week pre-shipment test. Performance could be verified through routine statistical process control (SPC).


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APPENDIX 1SCALING MODELSNOTICE: The material in this Appendix is an official part of SEMI M49 and was approved by full letter ballot procedures on [A&R approval date].

Table A1-1 Scaling Models Used in Table 3.1 for the Technology Nodes 130 to 65 nm


Nominal Nominal Nominal

1.1 Thickness (200 mm wafers), m 725 no scaling no scaling1.2 Thickness (300 mm wafers), m 775 no scaling no scaling1.3 Thickness (450 mm wafers), m 925 no scaling no scaling1.4 GBIR, nm 1000 no scaling no scaling1.5 Site Size local flatness, mm2 25 × 25 26 × 8 26 × 8

1.5.1 SBIR, including partial sites, nm 250 2/3 of (120 nm + max. SFQR per ITRS)#1

2/3 of (120 nm + max. SFQR per ITRS)#1

1.5.2 SFQR, including partial sites, nm 130 2/3 of max value acc. to per ITRS#2

2/3 of max value per ITRS#2

1.6 Warp, m 30 no scaling no scaling1.7 Nanotopography, 2 mm, P-V, nm, at 0.05% defective area 20 2/3 of max value acc to per

ITRS#22/3 of max value per

ITRS#2

1.8 Nanotopography, 10 mm, P-V, nm, at 0.05% defective area 70 70% of previous generation#3 70% of previous

generation#3

#1 120 nm is calculated to be the average taper contribution to SBIR for 130 nm node (SBIR–SFQR). This value is kept constant for the 90 and 65 nm technology nodes.#2 ITRS provides starting material technology requirements. The value given is assumed to be equivalent to the upper end of range recommended for reference wafers as defined in ¶ 5.5.17 and ¶ 5.5.18 . The nominal value is then 2/3 of the maximum value.#3 ITRS does not include starting materials technology requirement for nanotopography using 10 mm × 10 mm analysis area.

Table A1-2 Scaling Models Used in Table 4.1 for the Technology Nodes 45 to 2216 nm


16nm Node

Nominal Nominal NominalNominal

1.1 Thickness (200 mm wafers), m no scaling no scaling no scaling no scaling



1.4 GBIR, nm no scaling no scaling no scaling no scaling

1.5 Site Size local flatness, mm2 26 × 8 26 × 8 26 × 8 26 × 8

1.5.1 SBIR, including partial sites, nm2/3 of (120 nm + max. SFQR per

ITRS)#1

2/3 of (120 nm + max. SFQR per

ITRS)#1


ITRS)#1


ITRS) #1

1.5.2 SFQR, including partial sites, nm

2/3 of max value acc to per ITRS#2

2/3 of max value acc. to per ITRS#2

2/3 of max value acc. to per ITRS#2

2/3 of max value per ITRS #2

1.6 Warp, m no scaling no scaling no scaling no scaling

1.7 Nanotopography, 2 mm, P-V, nm, at 0.05% defective area



2/3 of max value acc.to perITRS#2

2/3 of max value per ITRS #2


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Date: 5/7/23


16nm Node

Nominal Nominal NominalNominal

1.8 Nanotopography, 10 mm, P-V, nm, at 0.05% defective area

(1/√2) of previous generation # 370% of

previous generation#3

(1/√2) of previous generation #3 70% of


(1/√2) of previous generation #3 70% of


(1/√2) of previous generation #3

1.9 ESFQR, nm72 sectors (θs = 5º), LR = 30 mm

125#4

EE=1mm


70% of previous generation#4

EE=1mm


70% of previous generation#4

EE=1mm


EE=1mm

1.10 ZDD, nm/mm2

16 sectors (θs = 22.5º)

−100#5

at radius Rnom – 2 mm

(1/√2)of previous generation 70% of



(1/√2)of previous generation 70% of


at radius Rnom – 2 mm or

−500#5


(1/√2)of previous generation at radius Rnom – 2 mm and at radius Rnom – 1

mm

#1 120 nm is calculated to be the average taper contribution to SBIR for 130 nm node (SBIR–SFQR). This value is kept constant for the 90, 65, 45, 32,22 and 2216 nm technology generations.#2 ITRS provides starting material technology requirements. The value given is assumed to be equivalent to the upper end of range recommended for reference wafers as defined in ¶ 5.5.17 and ¶ 5.5.18 . The nominal value is then 2/3 of the maximum value.#3 ITRS does not include starting materials technology requirement for nanotopography of 10 mm analysis area.#4 ITRS does not include materials technology requirement for near-edge geometry (ERO). The value for ESFQR at the 45 nm node is common industry practice; the 32 nm, 22 nm and 2216 nm values are scaled.#5 ITRS does not include materials technology requirement for near-edge geometry (ERO). The value for ZDD at the 45 nm node (at radius Rnom

– 2 mm at r1 = 2 mm) is common industry practice; the 32 nm smaller edge exclusion values at radius Rnom – 2 mm at r1 = 2 mm are scaled. For the 22 and 16nm node reference values are provided for both radius Rnom – 2 mm at r1 = 1 2mm and radius Rnom – 1 mm r1 = 21 mm. The 22 nm value at radius Rnom – 1 mm at r1 = 1 mm reflects the change to smaller edge exclusion.#6 When ERO values are added to the ITRS tables, the corresponding values in this document will be reviewed.

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