vhdl programs

ASYNCHRONOUS COUNTER

OBJECTIVE: To Design and Simulate the asynchronous upcounter.

VHDL CODE:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity asyn is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); qbar : inout STD_LOGIC_VECTOR (3 downto 0));end asyn;

architecture Behavioral of asyn is

component tff is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC :='1'; qbar : inout STD_LOGIC :='0');end component;

begin

tff1:tff port map('1',clk,q(0),qbar(0)); tff2:tff port map('1',q(0),q(1),qbar(1)); tff3:tff port map('1',q(1),q(2),qbar(2)); tff4:tff port map('1',q(2),q(3),qbar(3));

end Behavioral;

8.BCD TO EXCESS-3

OBJECTIVE: To Design and Simulate the bcd to excess3.

VHDL CODE:


entity bcdexcess3 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; x : out STD_LOGIC; y : out STD_LOGIC; z : out STD_LOGIC; w : out STD_LOGIC);end bcdexcess3;

architecture Behavioral of bcdexcess3 isbegin x<=not d; y<=(c and d)or (not(c or d)); z<=b xor (c or d); w<=(a or(b and(c or d)));end Behavioral;

BINARY TO GRAY CODE

OBJECTIVE: To Design and Simulate the binary to gray code.

VHDL CODE:


entity bcd2gray is Port ( b3 : in STD_LOGIC; b2 : in STD_LOGIC; b1 : in STD_LOGIC; b0 : in STD_LOGIC; g3 : out STD_LOGIC; g2 : out STD_LOGIC; g1 : out STD_LOGIC; g0 : out STD_LOGIC);end bcd2gray;

architecture Behavioral of bcd2gray isbegin g3<=b3; g2<=b3 xor b2; g1<=(not b1 and b2); g0<=b1 xor b0;end Behavioral;

4 BIT PARALLELI ADDER

OBJECTIVE: To Design and Simulate the 4 bit parallel adder.

VHDL CODE:


entity bit4adder is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); cin : in STD_LOGIC; sum : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC);end bit4adder;

architecture Behavioral of bit4adder iscomponent fa is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; s : out STD_LOGIC; car : out STD_LOGIC);end component;signal c1,c2,c3:std_logic;begin fa1:fa port map(a(0),b(0),cin,sum(0),c1); fa2:fa port map(a(1),b(1),c1,sum(1),c2); fa3:fa port map(a(2),b(2),c2,sum(2),c3); fa4:fa port map(a(3),b(3),c3,sum(3),cout);end Behavioral;

8 BIT PARALLEL ADDER

OBJECTIVE: To Design and Simulate the 8 bit parallel adder.

VHDL CODE:


entity bit8add is Port ( a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); cin : in STD_LOGIC; sum : out STD_LOGIC_VECTOR (7 downto 0); cout : out STD_LOGIC);end bit8add;architecture Behavioral of bit8add iscomponent fa is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; s : out STD_LOGIC; car : out STD_LOGIC);end component;signal c1,c2,c3,c4,c5,c6,c7:std_logic;begin fa1:fa port map(a(0),b(0),cin,sum(0),c1); fa2:fa port map(a(1),b(1),c1,sum(1),c2); fa3:fa port map(a(2),b(2),c2,sum(2),c3); fa4:fa port map(a(3),b(3),c3,sum(3),c4); fa5:fa port map(a(4),b(4),c4,sum(4),c5); fa6:fa port map(a(5),b(5),c5,sum(5),c6); fa7:fa port map(a(6),b(6),c6,sum(6),c7); fa8:fa port map(a(7),b(7),c7,sum(7),cout);end Behavioral;

6.3X8 DECODER

OBJECTIVE: To Design and Simulate the 3x8 decoder.

VHDL CODE:


entity dec3x8 is Port ( a : in STD_LOGIC_VECTOR (2 downto 0); en : in STD_LOGIC; y : out STD_LOGIC_VECTOR (7 downto 0));end dec3x8;

architecture Behavioral of dec3x8 isbegin process(a,en) begin if en='1' then y(7)<=not(a(0)and a(1) and a(2)); y(6)<=not(a(0)and a(1) and not a(2)); y(5)<=not(a(0)and not a(1) and a(2)); y(4)<=not(a(0)and not a(1) and not a(2)); y(3)<=not(not a(0)and a(1) and a(2)); y(2)<=not(not a(0)and a(1) and not a(2)); y(1)<=not(not a(0)and not a(1) and a(2)); y(0)<=not(not a(0)and not a(1) and not a(2)); else y<="00000000"; end if; end process;end Behavioral;

4X16 DECODER

OBJECTIVE: To Design and Simulate the 4x16 decoder.

VHDL CODE:


entity dec4x16 is Port ( a : in STD_LOGIC_VECTOR (2 downto 0); enable : in STD_LOGIC; y : out STD_LOGIC_VECTOR (15 downto 0));end dec4x16;

architecture Behavioral of dec4x16 iscomponent dec3x8 is Port ( a : in STD_LOGIC_VECTOR (2 downto 0); en : in STD_LOGIC; y : out STD_LOGIC_VECTOR (7 downto 0));end component;component notgate is Port ( a : in STD_LOGIC; b : out STD_LOGIC);end component;signal s1:std_logic;begin dec1:dec3x8 port map(a(2 downto 0),enable,y(7 downto 0)); dec2:dec3x8 port map(a(2 downto 0),s1,y(15 downto 8)); notgate1:notgate port map(enable,s1);end Behavioral;

DECADE COUNTER

OBJECTIVE: To Design and Simulate the decade counter.

VHDL CODE:


entity deccounter is Port ( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); qbar : inout STD_LOGIC_VECTOR (3 downto 0));end deccounter;

architecture Behavioral of deccounter iscomponent jkff2 is Port ( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC :='1'; qbar : inout STD_LOGIC :='0');end component;component andgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC);end component;signal s1:std_logic;begin jk1:jkff2 port map('1','1',clk,q(0),qbar(0)); jk2:jkff2 port map(qbar(3),'1',q(0),q(1),qbar(1)); jk3:jkff2 port map('1','1',q(1),q(2),qbar(2)); jk4:jkff2 port map(s1,'1',q(0),q(3),qbar(3)); andgate1:andgate port map(q(1),q(2),s1);end Behavioral;

D FLIP FLOP

OBJECTIVE: To Design and Simulate the d flip flop.

VHDL CODE:


entity dflop is Generic( td_reset, td_in: time:=8ns);

Port ( reset : in STD_LOGIC; din : in STD_LOGIC; clk : in STD_LOGIC; qout : buffer STD_LOGIC :='0');end dflop;

architecture Behavioral of dflop isbegin process(clk)

begin if (clk ='0' and clk'event) then if reset = '1' then qout<= '0' after td_reset; else qout<= din after td_in; end if; end if;

end process;end Behavioral;

HALF ADDER

OBJECTIVE: To Design and Simulate the half adder.

VHDL CODE:


entity ha is Port ( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; car : out STD_LOGIC);end ha;

architecture Behavioral of ha is

begin s<=a xor b; car<= a and b;end Behavioral;

JK FLIP FLOP

OBJECTIVE: To Design and Simulate the jk flip flop.VHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity jkff2 is Port ( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC :='1'; qbar : inout STD_LOGIC :='0');end jkff2;architecture Behavioral of jkff2 isbegin process(clk,j,k) begin if clk='0' and clk'event then if j='0' and k='0' then qbar<=not q; q<=q; end if; if j='0' and k='1' then qbar<='1'; q<='0'; end if; if j='1' and k='0' then qbar<='0'; q<='1'; end if;

if j='1' and k='1' then qbar<=q; q<=not q; end if; end if; end process;end Behavioral;

4X1 MULTIPLEXER

OBJECTIVE: To Design and Simulate the 4x1 multiplexer.

VHDL CODE:


entity mux4x1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC);end mux4x1;

architecture Behavioral of mux4x1 is

begin process(a,b,c,d,sel) variable temp:std_logic; begin case sel is when "00"=>temp:=a; when "01"=>temp:=b; when "10"=>temp:=c; when others=>temp:=d; end case; y<=temp; end process;end Behavioral;

SYNCHRONOUS COUNTER

OBJECTIVE: To Design and Simulate the synchronous counter.

VHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity syncntr is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); qbar : inout STD_LOGIC_VECTOR (3 downto 0));end syncntr;

architecture Behavioral of syncntr iscomponent tff is Port ( t : in STD_LOG; clk : in STD_LOGIC; q : inout STD_LOGIC :='1'; qbar : inout STD_LOGIC :='0');end component;component andgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC);end component;signal s1,s2,s3:std_logic;begin tff1:tff port map('1',clk,q(0),qbar(0)); tff2:tff port map(s1,clk,q(1),qbar(1)); tff3:tff port map(s2,clk,q(2),qbar(2)); tff4:tff port map(s3,clk,q(3),qbar(3)); and1:andgate port map('1',q(0),s1); ands:andgate port map(s1,q(1),s2); andq:andgate port map(s2,q(2),s3);end Behavioral;

T FLIP FLOP

OBJECTIVE: To Design and Simulate the t flip flop.

VHDL CODE:


entity tff is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC :='1'; qbar : inout STD_LOGIC :='0');end tff;

architecture Behavioral of tff isbegin process(clk,t) begin if clk='0' and clk'event then if t='0' then qbar<=not q; q<=q; end if; if t='1' then qbar<=q; q<=not q; end if; end if; end process;end Behavioral;

UP DOWN COUNTER

OBJECTIVE: To Design and Simulate the up down counter.

VHDL CODE:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity updncntr is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; up:in STD_LOGIC; dn:in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); qbar : inout STD_LOGIC_VECTOR (3 downto 0));end updncntr;

architecture Behavioral of updncntr iscomponent tff is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC :='1'; qbar : inout STD_LOGIC :='0');end component;component andgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC);end component;component orgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC);end component;signal s1,s2,s3,s4,s5,s6,s7,s8,s9:std_logic;

begin tff1:tff port map('1',clk,q(0),qbar(0)); tff2:tff port map('1',s3,q(1),qbar(1)); tff3:tff port map('1',s6,q(2),qbar(2)); tff4:tff port map('1',s9,q(3),qbar(3)); andgate1:andgate port map(q(0),up,s1); andgate2:andgate port map(qbar(0),dn,s2); andgate3:andgate port map(q(1),up,s4); andgate4:andgate port map(qbar(1),dn,s5); andgate5:andgate port map(q(2),up,s7); andgate6:andgate port map(qbar(2),dn,s8); orgate1:orgate port map(s1,s2,s3); orgate2:orgate port map(s4,s5,s6); orgate3:orgate port map(s7,s8,s9);end Behavioral;

--//binary ripple counter 7493

library ieee;use ieee.std_logic_1164.all;entity ic7493 isport(clk,r1,r2:in std_logic;

q1,q2,q3,q4:out std_logic);end ic7493;

architecture bincount of ic7493 iscomponent jkff port(j,k,clk,set,clr:in std_logic;

q:buffer std_logic);end component;signal cl,q11,q22,q33,q44:std_logic;signal one:std_logic;begin

one <= '1';cl <= not(r1 and r2);q1<=q11;q2<=q22;q3<=q33;q4<=q44;

u1 : jkff port map ( one,one,clk,one,cl,q11 ) ; u2 : jkff port map ( one,one,q11,one,cl,q22 ) ; u3 : jkff port map ( one,one,q22,one,cl,q33 ) ; u4 : jkff port map ( one,one,q33,one,cl,q44 ) ;

end bincount;

--//decade counter 7490

library ieee;use ieee.std_logic_1164.all;entity ic7490 isport(clk,s1,s2,r1,r2:in std_logic;

q1,q2,q3,q4:out std_logic);end ic7490;

architecture decount of ic7490 iscomponent jkff port(j,k,clk,set,clr:in std_logic;

q:buffer std_logic);end component;component rsff port(r,s,clk,set,clr:in std_logic;

q:buffer std_logic);end component;

signal se,cl,q11,q22,q33,q44:std_logic;signal one,qb44,q55:std_logic;begin

one <= '1';se <= not(s1 and s2);qb44<=not(q44);q55<=q22 and q33;cl <= not(r1 and r2);q1<=q11;q2<=q22;q3<=q33;q4<=q44;

u1 : jkff port map ( one,one,clk,se,cl,q11 ) ; u2 : jkff port map ( qb44,one,q11,se,cl,q22 ) ; u3 : jkff port map ( one,one,q22,se,cl,q33 ) ; u4 : rsff port map ( q44,q55,q11,se,cl,q44 ) ;

end decount;

universal shift register ic74195

library ieee;use ieee.std_logic_1164.all;--use ieee.std_logic_unsigned.all;--use ieee.std_logic_arith.all;--use ieee.numeric_std.all;entity ic74195 isport(j,kbar,a,b,c,d,sh_ld,clk,clbar:in std_logic;

qa,qb,qc,qd,qdbar:buffer std_logic);end ic74195;

architecture unisftrg of ic74195 iscomponent rsff port(r,s,clk,set,clr:in std_logic;

q:buffer std_logic);end component;

signal da,db,dc,dd,clkbar:std_logic;signal dba,dbb,dbc,dbd,one:std_logic;begin

one <= '1';clkbar <= not(clbar and clk);da<= not((sh_ld and j and not(qa))or(sh_ld and kbar and

qa)or(not(sh_ld) and a));db<= not((sh_ld and qa)or(not(sh_ld) and b));dc<= not((sh_ld and qb)or(not(sh_ld) and c));dd<= not((sh_ld and qc)or(not(sh_ld) and d));

qdbar<=not(qd);dba<=not(da);dbb<=not(db);dbc<=not(dc);dbd<=not(dd); u1 : rsff port map ( da,dba,clkbar,one,clbar,qa ) ; u2 : rsff port map ( db,dbb,clkbar,one,clbar,qb ) ; u3 : rsff port map ( dc,dbc,clkbar,one,clbar,qc ) ; u4 : rsff port map ( dd,dbd,clkbar,one,clbar,qd ) ;

end unisftrg;

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