VHDL TUTORIAL

S.M.K.Rahman

From:

ALTERA “ VHDL CLASS TUTORIAL”

What is VHDL?What is VHDL?

• IEEE Industry Standard hardware

description language

• Description language for both simulation

and synthesis

• Offshoot of Very High Speed Integrated

Circuit (VHSIC) DOD program in early

1980s

VHDL Synthesis vs. other HDLs VHDL Synthesis vs. other HDLs SynthesisSynthesis

• VHDL: Tell me how your circuit should behave and I will give you hardware that does the job

• ABEL, PALASM, AHDL:– Tell me what hardware you want and I will give it

to you

VHDL Synthesis vs. other HDL SynthesisVHDL Synthesis vs. other HDL Synthesis

Example of difference:

• VHDL: Give me a circuit whose output only changes when there is a low to high transition on a particular input. When that transition happens, make the output equal to the input until the next transition.

• Result: VHDL Synthesis gives you a positive edge triggered flip-flop

• Others: Give me a D-type flip-flop.

• Result: Synthesis gives you a D-type flip-flop. The sense of the clock depends on the synthesis tool.

EntityEntity• Defines interface to outside world, i.e input and output pins

• Serves same function as a schematic symbol

ENTITY example ISPORT ( a : in BIT;

b : out BIT);END example;

Inputs

Outputs

PortsPorts

• Defined in ENTITY

• Ports can be IN, OUT, INOUT

ArchitectureArchitecture• Defines implementation of design, i.e. logic equations

• Serves same function as a schematic

ARCHITECTURE pld OF example ISBEGIN

b <= a;END pld;

Logic equations go between BEGIN andEND

Example of Complete DesignExample of Complete Design

ENTITY example IS

PORT ( a : in BIT;b : out BIT);

END example;

ARCHITECTURE pld OF example ISBEGIN

b <= a;END pld;

ENTITY defines ports of design

ARCHITECTURE defines implementation

ENTITY and ARCHITECTUREmake a pair linked by name

PROCESS StatementPROCESS Statement

• Groups sequential statements

• WAIT Statement or Sensitivity list

describes conditions for executing

PROCESS

• Within the process, statements are

executed sequentially

PROCESS Statement PROCESS Statement

This process is executedafter a change in anysignal in the Sensitivity List

PROCESS (sensitivity_list)BEGIN

-- Sequential statement #1-- .....-- Sequential statement #N

END PROCESS;

Using the Sensitivity List

PROCESS StatementPROCESS Statement

PROCESSBEGIN

WAIT condition-- Sequential statement #1-- .....-- Sequential statement #N

END PROCESS;This process is executed when the WAIT conditionis true!

Using the WAIT statement:

PROCESS StatementPROCESS Statement

Use LABELS for organization:

label: PROCESS (sensitivity list)BEGIN

-- Sequential statement #1-- .....-- Sequential statement #2

END PROCESS label;

The label identifies specific processes in a multi-process architecture

Signal Assignment ExamplesSignal Assignment Examples

• Simple

• Conditional

• Selected

q <= r or t;

q <= ‘0’ WHEN clr = ‘0’ ELSE

‘1’ WHEN set = ‘1’ ELSE ‘X’;

WITH sel SELECTq <= a WHEN ‘0’

b WHEN ‘1’

q <= ((r or t) and not(g xor h));

IF StatementIF Statement

• Chooses action based on condition

• Allows ELSIF, ELSE statements

• Must be inside PROCESS

?

IF Statement ExampleIF Statement ExampleENTITY if_ex IS

PORT ( sel, a, b : in BIT; y : out BIT );

END if_ex;

ARCHITECTURE if_ex OF if_ex ISBEGIN PROCESS (sel, a, b) BEGIN

IF sel = '1' THEN y <= a;ELSE y <= b;END IF;

END PROCESS;END if_ex;

process is sensitive to all inputs used insideprocess

This circuit results ina multiplexer

VHDL VariablesVHDL VariablesENTITY var_ex IS

PORT ( x, a, b :IN BIT;

z :OUT BIT);

END var_ex;

ARCHITECTURE example OF var_ex IS

BEGIN

PROCESS (x, a, b)

VARIABLE tmp :BIT ;

BEGIN

IF (x = '1') THEN

tmp := a AND b;

z <= tmp;

ELSE

z <= '1';

END IF;

END PROCESS;

END example;

VARIABLE “tmp” holdsintermediate value

Resulting SchematicResulting Schematic

VHDL SignalsVHDL SignalsENTITY sig_ex IS PORT ( a, b, c :IN BIT; y :OUT BIT);END sig_ex; ARCHITECTURE example OF sig_ex IS

SIGNAL temp :BIT; BEGIN

temp <= a XOR b;y <= temp AND c;

END example;

This SIGNAL is usedto interconnect primitives

Resulting SchematicResulting Schematic

VHDL SignalsVHDL SignalsENTITY mul IS

PORT (a, b, c, selx, sely : IN BIT; data_out : OUT BIT);

END mul;

ARCHITECTURE ex OF mul ISSIGNAL temp : BIT;BEGIN

process_a: PROCESS (a, b, selx)BEGIN

IF (selx = ‘0’ THENtemp <= a;

ELSE temp <= b;

END IF;END PROCESS process_a;

process_b: PROCESS(temp, c, sely)

BEGIN

IF (sely = ‘0’ THEN

data_out <= temp;

ELSE

data_out <= c;

END IF;

END PROCESS process_b;

END ex;

SIGNAL temp is used here to connectmultiple processes

Resulting SchematicResulting SchematicProcesses interconnected bySIGNAL temp

Generated from process_a

Generated from process_b

Signals vs. VariablesSignals vs. Variables

Represent Circuit Represent local storage

Interconnect

Global Scope (anywhere) Local Scope

(inside process)

Updated at end of PROCESS Updated Immediately(new value not available) (new value available)

SIGNALS VARIABLES

UTILITY:

SCOPE:

BEHAVIOR:

Signals vs. VariablesSignals vs. Variables

Correct Use (VARIABLE)ENTITY good IS

PORT (i0, i1, i2, i3, a, b: IN BIT; q : OUT BIT);

END good;ARCHITECTURE right OF good ISBEGINPROCESS (i0, i1, i2, i3, a, b)

VARIABLE val: INTEGER RANGE 0 TO 3;

BEGINval := 0;IF (a = ‘1’ THEN

val := val + 1;END IF;

IF (b = ‘1’ THENval := val + 2;

END IF;CASE val IS

WHEN 0 =>q < = i0;WHEN 1 =>q <= i1;WHEN 2 =>q <= i2;WHEN 3 =>q <= i3;

END CASEEND PROCESS;

END right;

Examples of Differences

New valueis available

Signals vs. VariablesSignals vs. VariablesIncorrect Use (SIGNAL)ENTITY bad IS

PORT (i0, i1, i2, i3, a, b : IN BIT; q : OUT BIT);

END bad;

ARCHITECTURE wrong OF bad ISSIGNAL val : INTEGER RANGE

0 TO 3;BEGIN PROCESS (i0, i1, i2, i3, a, b)BEGIN

val <= 0;IF (a = ‘1’ THEN

val <= val + 1;END IF;

IF (b = ‘1’ THENval <= val + 2;

END IF;CASE val IS

WHEN 0 =>q <= i0;

WHEN 1 =>q <= i1;

WHEN 2 =>q <= i2;

WHEN 3 =>q <= i3;

END CASE;END PROCESS;END wrong;

Examples of Differences

New value is not yet available

Non-Combinatorial Use of Non-Combinatorial Use of VariableVariable

ENTITY unsynth IS PORT ( sela, selb :IN BIT;

dout :OUT BIT);END unsynth;

ARCHITECTURE example OF unsynth ISBEGINPROCESS (sela, selb)

VARIABLE temp : BIT ;BEGIN

IF (sela = '1') THENtemp := '1';

ELSIF (selb = '1') THENtemp := '0';

END IF;dout <= temp;

END PROCESS;END example;

temp keeps old value if sela = ‘0’and selb = ‘0’

This defines a latch, not a combinatorial circuit.

Internal variables should beassigned on every pass through a process!

Data TypesData Types• VHDL is a strongly typed language, i.e disparate data types may not

be assigned to each other

• All ports, signals, variables must be of some type

• Built-in types, or create your own

Data TypesData Types

• Simplest type is BIT

• BIT can have the values {‘0’,’1’}

• What about tri-states?

STD_LOGIC Data TypeSTD_LOGIC Data Type

• Another common type

• std_logic = {‘0’,’1’,’X’,’Z’} and 5 others not used

for synthesis

• ‘X’ used for unknown

• ‘Z’ (not ‘z’) used for tristate

INTEGER Data TypeINTEGER Data Type• Behaves like an integer in algebra• Range is user-specified or compiler-

default – User can specify any subrange

fred :INTEGER range 0 to 255;

– If range is not specified it will be the compiler-dependent default

fred :INTEGER;

Bus ImplementationBus Implementation

• VHDL offers vector types to implement buses• Common vector types are: bit_vector,

std_logic_vector• Examples:

SIGNAL fred_bus :bit_vector (7 downto 0);

SIGNAL barney_bus :std_logic_vector (3 downto 0);

SIGNAL betty_bus :std_logic_vector (0 to 3);

Bus AssignmentBus Assignment

• Reference entire bus fred_bus <= “11111111”;

• Reference one bit of a bus bus (3) <= ‘1’;

• Reference a slice of the bus bus (3 downto 2) <= “11”;

Enumerated TypesEnumerated Types• Enumerated types are the most common user-

created types• Enumerated types are used primarily for state

machines

Example:

TYPE country IS (Germany, USA, Italy, Japan);

TYPE state_type IS (state_a, state_b, state_c);

VHDL PACKAGEsVHDL PACKAGEsWhat are packages?

• Packages are a collection of elements including data type descriptions

• They can be shared by multiple designs/designers

• You can use standard packages which are included with VHDL or create your own

VHDL PackagesVHDL PackagesCommonly Used Packages:

• IEEE.std_logic_arith - arithmetic functions

• IEEE.std_logic_signed - signed arithmetic functions

• IEEE.std_logic_unsigned - unsigned arithmetic functions

• IEEE.std_logic_1164 - std_logic and related functions

• ALTERA.maxplus2 - component declarations for all

Altera macrofunctions

How to use a packageHow to use a package• LIBRARY <library name>;• USE <library name>.<package name>.all;• In MAX+PLUS II, <library name> is a

subdirectory of c:\maxplus2\max2vhdl• Library name is IEEE, ALTERA• Can specify a particular element instead of all

Library

Package

individual itemsor .all

Packages in MAX+PLUS IIPackages in MAX+PLUS IIExample:

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

USE IEEE.std_logic_arith.all;

USE IEEE.std_logic_unsigned.all;

LIBRARY altera;

USE altera.maxplus2.all;

User-defined PackageUser-defined Package

• User-defined packages must be in the same directory as the design

• To use your new packages:

LIBRARY WORK;

USE WORK.<package name>.all;

CASE StatementsCASE Statements• Used to generate combinatorial logic• Must specify all possibilities with a “WHEN

OTHERS” statement

CASE val ISWHEN “00” =>

q <= i0;WHEN “01” =>

q <= i1;WHEN OTHERS =>

q <= ‘X’;END CASE;

val and i0, i1 will beinput to combinatoriallogic

q will be output tocombinatorial logic

Operator Overloading: Why and Operator Overloading: Why and What?!?What?!?

• VHDL defines arithmetic and boolean functions only for built-in data types: – Arithmetic Operators such as +, -, <, >, <=, >= work

for the INTEGER type– Boolean Operators such as AND, OR, NOT work only

with BIT type

• How do you use arithmetic and boolean functions with other data types?– Operator Overloading

Operator Overloading: How is it implementedOperator Overloading: How is it implemented??

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;

ENTITY overload IS PORT ( a : IN std_logic_vector (3 downto 0); b : IN std_logic_vector (3 downto 0); sum : OUT std_logic_vector (4 downto 0));

END overload;

ARCHITECTURE example OF overload ISBEGINadder_body:PROCESS (a, b)BEGIN

sum <= a + b;END PROCESS adder_body;END example;

Include these statementsat the beginning of each design file.

This allows us to performarithmetic on non-built-in data types.

Synthesis RulesSynthesis Rules

• Not all processes are synthesizable• To be synthesizable, one of these must be true:

Combinatorial circuit: Sensitive to all input signals

Registered circuit: Sensitive to a single clock edge and optional asynchronous

clear/preset/load signals

Latch InferenceLatch Inference• VHDL code describes behavior of transparent latch

• PROCESS is sensitive to both Data and Gate

• Notice similarity to mux

PROCESS (Data, Gate)BEGIN

IF Gate = ??THENQ <= Data;

END IF;END PROCESS;

Flip-Flop Flip-Flop InferenceInference• VHDL code describes behavior of D-Type

Flip-Flop

• This implementation uses PROCESS

sensitivity list

• Clock is only signal in sensitivity listPROCESS (clk)BEGIN

IF clk = 1 THENq <= d;

END IF;END PROCESS;

Flip-Flop InferenceFlip-Flop Inference

• Implementation using PROCESS with WAIT statement PROCESS

BEGIN WAIT UNTIL clk = ‘1’

q <= d;END PROCESS;

Flip-Flop Inference with Flip-Flop Inference with Asynchronous ClearAsynchronous Clear

• Both Clock and Clear are in sensitivity list

• Why do we need the clk’EVENT?PROCESS (clock, clear)BEGIN

IF clear = ‘0’ THENq <= ‘0’;

ELSIF clock’EVENT and clock = ‘1’ THENq <= d;

END IF;END PROCESS;

Gated ClocksGated Clocks• Clock must be gated outside of PROCESS

description• Must define new clock as a signal

ARCHITECTURE ex OF gatedclock ISSIGNAL gclock : std_logic;BEGIN

gclock <= clka AND clkb;PROCESS (gclock)BEGIN

IF gclock = '1' THENq <= d;

END IF;END PROCESS;

END ex;

Clock is gated here

Then used here

Module GenerationModule Generation• The VHDL synthesizer generates modules for each

arithmetic function entered in a design• These modules are then converted to structures

that are optimized for the target device• Example:

Adder structure for FLEX is ripple-carryAdder structure for MAX is carry-look ahead

• Family-specific module generation is automatic

Module GenerationModule Generation

VHDL design file Module

a <= b + c;

b

c

a

Gate-level Structures

FLEX

MAX

+

CountersCounters

• Counters are just accumulators that always add a ‘1’

ARCHITECTURE example OF counter ISBEGIN

PROCESS (clk)VARIABLE count : std_logic_vector (7 downto 0);BEGIN

IF clk = '1' THENcount := count + 1;END IF;

q <= count;END PROCESS;

END example;

CountersCounters• Add enable, load and up/down features with

IF statementsARCHITECTURE example OF counter ISBEGIN

PROCESS (clk)VARIABLE count : std_logic_vector (7 downto 0);BEGIN

IF clk = '1' THENIF ldn = '0' THEN

count := load;ELSE count := count + 1;END IF;

END IF;q <= count;END PROCESS;

END example;

Multiple Design FilesMultiple Design Files• VHDL allows hierarchical design through

component instantiationtop.vhdentity-architecture “top”component “mid_a”component “mid_b”

mid_a.vhdentity-architecture “mid_a”component “bottom_a”

mid_b.vhdentity-architecture “mid_b”component “bottom_a”component “bottom_b”

bottom_a.vhdentity-architecture “bottom_a”

bottom_b.vhdentity-architecture “bottom_b”

Component InstantiationComponent Instantiation• The Upper-level design must have a COMPONENT

declaration for a lower-level design before instantiating it

COMPONENT declared here

COMPONENT used here

ARCHITECTURE upper OF top ISSIGNAL count : std_logic;COMPONENT simpcnt PORT ( clk : IN bit;

q : OUT std_logic);END COMPONENT;BEGIN u1 : simpcnt PORT MAP (clk => sysclk, q => count);

Macrofunction and Primitive Macrofunction and Primitive LibrariesLibraries

• Silicon vendors often provide libraries of macrofunctions and primitives

• These can be used to control the physical implementation of the design within the programmable logic device

• Vendor specific libraries will improve the performance and efficiency of the design

• Altera provides a complete library of LPM compliant macrofunctions, plus other primitives

Macrofunction InstantiationMacrofunction Instantiation

• All of the Altera macrofunctions and primitive components are declared in the VHDL package:ALTERA.maxplus2.all

• Within this package, all component ports are of type STD_LOGIC or STD_LOGIC_VECTOR

Macrofunction InstantiationMacrofunction Instantiation

LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;LIBRARY ALTERA;USE ALTERA.maxplus2.ALL;ENTITY macro IS

PORT(clock, enable : IN std_logic;Qa, Qb, Qc, Qd : OUT std_logic);

END macro;ARCHITECTURE example OF macro ISBEGIN

u1 : gray4 PORT MAP (clk => clock, ena => enable, qa => Qa, qb => Qb, qc => Qc, qd => Qd);

END example;

Use the ALTERA library for macrofunction instantiationso that component declarationsare not needed.