6542285 Vhdl Programs
Transcript of 6542285 Vhdl Programs
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Priority Encoders
VHDL
Following is the VHDL code for a 3-bit 1-of-9 Priority Encoder.
library ieee;use ieee.std_logic_1164.all;
entity priority isport ( sel : in std_logic_vector (7 downto 0);
code :out std_logic_vector (2 downto 0));end priority;architecture archi of priority isbegincode
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VHDL (One-Cold)
Following is the VHDL code for a 3 to 8 line decoder.
library ieee;use ieee.std_logic_1164.all;
entity dec isport (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));end dec;architecture archi of dec isbeginres
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s[2:0] Selector
res Data Output
VHDL
Following is the VHDL code.
library ieee;use ieee.std_logic_1164.all;
entity dec isport (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));end dec;
architecture archi of dec isbeginres
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4-to-1 MUX Using CASE Statement
The following table shows pin definitions for a 4-to-1 1-bit MUX using a Case statement.
IO Pins Description
a, b, c, d Data Inputs
s[1:0] MUX selector
o Data Output
VHDL Code
Following is the VHDL code for a 4-to-1 1-bit MUX using a Case statement.
library ieee;
use ieee.std_logic_1164.all;
entity mux isport (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);o : out std_logic);
end mux;
architecture archi of mux isbeginprocess (a, b, c, d, s)begincase s iswhen "00" => o o o o
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VHDL Code
Following is the VHDL code for a 4-to-1 1-bit MUX using tristate buffers.
library ieee;use ieee.std_logic_1164.all;
entity mux isport (a, b, c, d : in std_logic;
s : in std_logic_vector (3 downto 0);o : out std_logic);
end mux;
architecture archi of mux isbegin
o
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end mux;architecture archi of mux isbeginprocess (a, b, c, d, s)beginif (s = "00") then o
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XST will not infer a Logical Shifter for this example, as not all of the selector values are
presented.
IO pins Description
D[7:0] Data Input
SEL shift distance selector
SO[7:0] Data Output
VHDL
Following is the VHDL code.
library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lshift isport(DI : in unsigned(7 downto 0);
SEL : in unsigned(1 downto 0);SO : out unsigned(7 downto 0));
end lshift;architecture archi of lshift isbeginwith SEL selectSO
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use ieee.numeric_std.all;
entity lshift isport(DI : in unsigned(7 downto 0);
SEL : in unsigned(1 downto 0);SO : out unsigned(7 downto 0));
end lshift;architecture archi of lshift isbeginwith SEL selectSO
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The following table shows pin descriptions for an unsigned 8-bit Adder.
IO pins Description
A[7:0], B[7:0] Add Operands
SUM[7:0] Add Result
VHDL
Following is the VHDL code for an unsigned 8-bit Adder.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity adder isport(A,B : in std_logic_vector(7 downto 0);
SUM : out std_logic_vector(7 downto 0));end adder;architecture archi of adder isbeginSUM
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CI : in std_logic;SUM : out std_logic_vector(7 downto 0));
end adder;architecture archi of adder isbeginSUM
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Unsigned 8-bit Adder with Carry In and Carry Out
This section contains VHDL and Verilog code for an unsigned 8-bit adder with Carry In
and Carry Out.
The following table shows pin descriptions for an unsigned 8-bit adder with carry.
IO pins Description
A[7:0], B[7:0] Add Operands
CI Carry In
SUM[7:0] Add Result
CO Carry Out
VHDL
Following is the VHDL code for an unsigned 8-bit adder with carry in and carry out.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;
entity adder isport(A,B : in std_logic_vector(7 downto 0);
CI : in std_logic;SUM : out std_logic_vector(7 downto 0);
CO : out std_logic);end adder;architecture archi of adder issignal tmp: std_logic_vector(8 downto 0);begintmp
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SUM[7:0] Add Result
VHDL
Following is the VHDL code for a simple signed 8-bit adder.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;
entity adder isport(A,B : in std_logic_vector(7 downto 0);
SUM : out std_logic_vector(7 downto 0));end adder;architecture archi of adder isbeginSUM
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IO pins Description
A[7:0], B[7:0] Add/Sub Operands
OPER Add/Sub Select
SUM[7:0] Add/Sub Result
VHDL
Following is the VHDL code for an unsigned 8-bit adder/subtractor.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity addsub isport(A,B : in std_logic_vector(7 downto 0);
OPER: in std_logic;RES : out std_logic_vector(7 downto 0));end addsub;architecture archi of addsub isbeginRES
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entity compar isport(A,B : in std_logic_vector(7 downto 0);
CMP : out std_logic);end compar;architecture archi of compar isbeginCMP = B
else '0';end archi;
Multipliers
When implementing a multiplier, the size of the resulting signal is equal to the sum of 2
operand lengths. If you multiply A (8-bit signal) by B (4-bit signal), then the size of the
result must be declared as a 12-bit signal.
Unsigned 8x4-bit Multiplier
This section contains VHDL and Verilog descriptions of an unsigned 8x4-bit multiplier.
The following table shows pin descriptions for an unsigned 8x4-bit multiplier.
IO pins Description
A[7:0], B[3:0] MULT Operands
RES[7:0] MULT Result
VHDL
Following is the VHDL code for an unsigned 8x4-bit multiplier.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity mult isport(A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(3 downto 0);RES : out std_logic_vector(11 downto 0));
end mult;architecture archi of mult isbeginRES
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Divisions are only supported, when the divisor is a constant and is a power of 2. In that
case, the operator is implemented as a shifter; otherwise, an error message will be issued
by XST.
Division By Constant 2
This section contains VHDL and Verilog descriptions of a Division By Constant 2
divider.
The following table shows pin descriptions for a Division By Constant 2 divider.
IO pins Description
DI[7:0] DIV Operands
DO[7:0] DIV Result
VHDL
Following is the VHDL code for a Division By Constant 2 divider.
library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;
entity divider isport(DI : in unsigned(7 downto 0);
DO : out unsigned(7 downto 0));end divider;
architecture archi of divider isbeginDO
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Example
For the following VHDL/Verilog example, XST will give the following solution:
The following table shows pin descriptions for the example.
IO pins Description
A[7:0], B[7:0], B[7:0] DIV Operands
OPER Operation Selector
RES[7:0] Data Output
VHDL
Following is the VHDL example for resource sharing.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity addsub isport(A,B,C : in std_logic_vector(7 downto 0);
OPER : in std_logic;RES : out std_logic_vector(7 downto 0));
end addsub;architecture archi of addsub isbeginRES
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LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;
ENTITY adder ISPORT(in1: IN std_logic_vector(15 DOWNTO 0) ;
in2: IN std_logic_vector(15 DOWNTO 0) ;c_out: OUT std_logic ;sum: OUT std_logic_vector(15 DOWNTO 0)
) ;END adder ;
ARCHITECTURE synthesizable OF adder ISBEGIN
PROCESS(in1, in2)VARIABLE tmp_in1: signed(16 DOWNTO 0) ;VARIABLE tmp_in2: signed(16 DOWNTO 0) ;VARIABLE output: signed(16 DOWNTO 0) ;VARIABLE c: std_logic ;
BEGIN
tmp_in1 := signed('0' & in1) ;tmp_in2 := signed('0' & in2) ;output := tmp_in1 + tmp_in2 ;IF (output(16) = '1') THEN
c := '1' ;ELSE
c := '0' ;END IF ;sum
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ELSIF (ld = '1') THENtmpvar := unsigned(input) ;
ELSIF (inc = '1') THENtmpvar := tmpvar + "000000000001" ;
END IF ;output
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SIGNAL output: OUT std_logic_vector(2 DOWNTO 0)) ;
END enc8to3 ;
---- Here is a case where we really need the WHEN - ELSE-- I don't think the WITH select will work because-- we want a priority encoder--ARCHITECTURE arch1 OF enc8to3 ISBEGIN
output
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USE ieee.std_logic_1164.all ;
ENTITY reg ISPORT(clk: IN std_logic ;
input: IN std_logic_vector(15 DOWNTO 0) ;output: OUT std_logic_vector(15 DOWNTO 0) ;ld: IN std_logic
) ;END reg ;
ARCHITECTURE behavioral OF reg ISBEGIN
generic_register: PROCESS(clk, input, ld)BEGIN
IF (rising_edge(clk)) THENIF (ld = '1') THEN
output
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if (clock='1' and clock'event) thendata_out
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case (input) iswhen "11" =>
state
state
state
null;end case;
end if;
end process;
-- concurrent statementsQ
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if clear = '0' then-- use 'range in signal assigmentQ_tmp
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end if;end if;
end process;
-- concurrent assignmentQ
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end process;
-- concurrent assignment statementQ
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The following table shows pin definitions for an 8-bit shift-left register with a positive-
edge clock, serial in, and serial out.
IO Pins Description
C Positive-Edge Clock
SI Serial In
SO Serial Output
VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
serial in, and serial out.
library ieee;
use ieee.std_logic_1164.all;
entity shift isport(C, SI : in std_logic;
SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='1') thenfor i in 0 to 6 looptmp(i+1)
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C Negative-Edge Clock
SI Serial In
CE Clock Enable (active High)
SO Serial Output
VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a negative-edge clock,
clock enable, serial in, and serial out.
library ieee;use ieee.std_logic_1164.all;
entity shift isport(C, SI, CE : in std_logic;
SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='0') thenif (CE='1') thenfor i in 0 to 6 looptmp(i+1)
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C Positive-Edge Clock
SI Serial In
CLR Asynchronous Clear (active High)
SO Serial Output
VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
asynchronous clear, serial in, and serial out.
library ieee;use ieee.std_logic_1164.all;
entity shift isport(C, SI, CLR : in std_logic;
SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C, CLR)beginif (CLR='1') thentmp '0');
elsif (C'event and C='1') thentmp
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S synchronous Set (active High)
SO Serial Output
VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,synchronous set, serial in, and serial out.
library ieee;use ieee.std_logic_1164.all;
entity shift isport(C, SI, S : in std_logic;
SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C, S)beginif (C'event and C='1') thenif (S='1') thentmp '1');
elsetmp
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VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
serial in, and serial out.
library ieee;use ieee.std_logic_1164.all;
entity shift isport(C, SI : in std_logic;
PO : out std_logic_vector(7 downto 0));end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='1') thentmp
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library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI, ALOAD : in std_logic;
D : in std_logic_vector(7 downto 0);SO : out std_logic);
end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C, ALOAD, D)beginif (ALOAD='1') thentmp
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entity shift isport(C, SI, SLOAD : in std_logic;
D : in std_logic_vector(7 downto 0);SO : out std_logic);
end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='1') thenif (SLOAD='1') thentmp
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signal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='1') thenif (LEFT_RIGHT='0') thentmp
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C Positive-Edge Clock
CLR Asynchronous Clear (active High)
Q[3:0] Data Output
VHDL Code
Following is VHDL code for a 4-bit unsigned up counter with asynchronous clear.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity counter isport(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));end counter;
architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);begin
process (C, CLR)beginif (CLR='1') thentmp
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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity counter isport(C, S : in std_logic;
Q : out std_logic_vector(3 downto 0));end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C)beginif (C'event and C='1') thenif (S='1') thentmp
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port(C, ALOAD : in std_logic;D : in std_logic_vector(3 downto 0);Q : out std_logic_vector(3 downto 0));
end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C, ALOAD, D)beginif (ALOAD='1') thentmp
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process (C)beginif (C'event and C='1') thenif (SLOAD='1') thentmp
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tmp
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tmp
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Registers
Flip-flop with Positive-Edge Clock
The following figure shows a flip-flop with positive-edge clock.
The following table shows pin definitions for a flip-flop with positive edge clock.
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IO Pins Description
D Data Input
C Positive Edge Clock
Q Data Output
VHDL Code
Following is the equivalent VHDL code sample for the flip-flop with a positive-edgeclock.
library ieee;use ieee.std_logic_1164.all;
entity flop isport(C, D : in std_logic;
Q : out std_logic);end flop;architecture archi of flop isbeginprocess (C)beginif (C'event and C='1') thenQ
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The following table shows pin definitions for a flip-flop with negative edge clock and
asynchronous clear.
IO Pins Description
D Data Input
C Negative-Edge Clock
CLR Asynchronous Clear (active High)
Q Data Output
VHDL Code
Following is the equivalent VHDL code for a flip-flop with a negative-edge clock and
asynchronous clear.
library ieee;use ieee.std_logic_1164.all;
entity flop isport(C, D, CLR : in std_logic;
Q : out std_logic);end flop;architecture archi of flop isbeginprocess (C, CLR)beginif (CLR = '1')thenQ
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The following figure shows a flip-flop with positive-edge clock and synchronous set.
The following table shows pin definitions for a flip-flop with positive edge clock andsynchronous set.
IO Pins Description
D Data Input
C Positive-Edge Clock
S Synchronous Set (active High)
Q Data Output
VHDL Code
Following is the equivalent VHDL code for the flip-flop with a positive-edge clock and
synchronous set.
library ieee;use ieee.std_logic_1164.all;
entity flop isport(C, D, S : in std_logic;
Q : out std_logic);end flop;architecture archi of flop isbeginprocess (C)beginif (C'event and C='1') thenif (S='1') thenQ
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Flip-flop with Positive-Edge Clock and Clock Enable
The following figure shows a flip-flop with positive-edge clock and clock enable.
The following table shows pin definitions for a flip-flop with positive edge clock and
clock enable.
IO Pins Description
D Data Input
C Positive-Edge Clock
CE Clock Enable (active High)
Q Data Output
VHDL Code
Following is the equivalent VHDL code for the flip-flop with a positive-edge clock and
clock Enable.
library ieee;use ieee.std_logic_1164.all;
entity flop isport(C, D, CE : in std_logic;
Q : out std_logic);end flop;architecture archi of flop isbeginprocess (C)begin
if (C'event and C='1') thenif (CE='1') thenQ
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4-bit Register with Positive-Edge Clock, Asynchronous Set and Clock
Enable
The following figure shows a 4-bit register with positive-edge clock, asynchronous setand clock enable.
The following table shows pin definitions for a 4-bit register with positive-edge clock,
asynchronous set and clock enable.
IO Pins Description
D[3:0] Data Input
C Positive-Edge Clock
PRE Asynchronous Set (active High)
CE Clock Enable (active High)
Q[3:0] Data Output
VHDL Code
Following is the equivalent VHDL code for a 4-bit register with a positive-edge clock,asynchronous set and clock enable.
library ieee;use ieee.std_logic_1164.all;
entity flop isport(C, CE, PRE : in std_logic;
D : in std_logic_vector (3 downto 0);Q : out std_logic_vector (3 downto 0));
end flop;architecture archi of flop isbeginprocess (C, PRE)beginif (PRE='1') thenQ
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Q
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process (G, D)beginif (G='1') thenQ
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end archi;
Unsigned 8-bit Greater or Equal Comparator
The following table shows pin descriptions for a comparator.
IO pins Description
A[7:0], B[7:0] Add/Sub Operands
CMP Comparison Result
VHDL
Following is the VHDL code for an unsigned 8-bit greater or equal comparator.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity compar isport(A,B : in std_logic_vector(7 downto 0);
CMP : out std_logic);end compar;
architecture archi of compar isbeginCMP = B
else '0';end archi;