THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf ·...

44
THE TIME-TRIGGERED ARCHITECTURE Authors: Herman Kopetz Gunther Bauer Presented By: Muhammad Umer Tariq Shez Virani

Transcript of THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf ·...

Page 1: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

THE TIME-TRIGGERED ARCHITECTURE

Authors:

Herman Kopetz

Gunther Bauer

Presented By:

Muhammad Umer Tariq

Shez Virani

Page 2: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Agenda

� Introduction

� Time Triggered Architecture’s Detail

� Principles that Guided the Design of TTA

� Communication Infrastructure of the TTA� Communication Infrastructure of the TTA

TTP/C protocol

TTP/A Protocol

� TTA Design Methodology

� Conclusion

Page 3: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Introduction

� Computer Architecture:

� A framework for the design of a class of computing system that share a common set of characteristics.

� Examples:� Examples:

� Digital Signal Processor(DSP)

� General Purpose Desktop Architectures

� Time Triggered Architecture (TTA)

� Framework for the domain of Large Distributed Embedded Real Time Systems in High Dependability Environment

Page 4: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Beyond Academics!

� Used by Alcatel in Safety Critical Train Control Applications (1999)

� Used by Honeywell for Flight Control applications (2000)

� Selected by Audi for its future “Drive by Wire” applications � Selected by Audi for its future “Drive by Wire” applications (2000)

Page 5: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Agenda

� Introduction

� Time Triggered Architecture’s Detail

� Principles that Guided the Design of TTA

� Communication Infrastructure of the TTA� Communication Infrastructure of the TTA

TTP/C protocol

TTP/A Protocol

� TTA Design Methodology

� Conclusion

Page 6: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Characteristics of TTA

� Decomposes a large embedded applications into clusters and nodes.

� Provides a fault tolerant global time base of known precision at every node.

Takes advantage of the availability of this global time to:� Takes advantage of the availability of this global time to:

� Precisely specify the interfaces among the nodes

� To simplify the communication and agreement protocols

� To perform prompt error detection

� To guarantee the timeliness of real time applications

Page 7: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common
Page 8: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Model of Time

� Real Time:

� Progresses along a dense timeline, consisting of an infinite set of instants, from the past to the future.

� Duration(Interval):Duration(Interval):

� A section of the timeline, delimited by two instants.

� Event:

� A happening that occurs at an instant (a cut of the timeline)

� Time Stamp of an Event:

� Established by assigning the state of the node-local global time to the event immediately after the event occurrence.

Page 9: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Model of Time

� Impossible to consistently order events on the basis of their global time stamps due to:

� Inability to synchronize clocks perfectly

� Denseness property of real time� Denseness property of real time

� Solution: Sparse Time Base

� The continuum of time is partitioned into an infinite sequence of alternating durations of activity and silence.

� The duration of the activity interval must be larger than the precision of the clock synchronization

Page 10: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Sparse Time Base

Page 11: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Sparse Time Base (Temporal Ordering)

� All events that happen within an interval of activity are concurrent

� Events that happen during different intervals of activity are separated by the required interval of silence and can therefore be consistently globally orderedbe consistently globally ordered

� Architecture must make sure that significant events, such as the sending of a message, occur only during an interval of activity.

� The time stamps of events that are outside the control of the distributed computer system must be assigned to an agreed duration of activity by an agreement protocol.

Page 12: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Time and State

� Notions of Time and State are inseparable!

� If an event that updates the state cannot be said to coincide with a well-defined tick of a global clock. It is not known whether the state of the system at a given clock tick includes this event or not.this event or not.

� Sparse Time Base makes it possible to define a system wide notion of time, and thus the definition of a system wide distributed state.

� Without Sparse Time Base, it becomes pretty difficult.

� (Remember the Mid Term!!!)

Page 13: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Time-Triggered Model

Page 14: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Real-Time Entities

� Think of putting some application on this distributed architecture!

� Dynamics of a real time application are modeled by a set of relevant state variables, the real time entities (RT entities) relevant state variables, the real time entities (RT entities)

e.g. Flow of a liquid in pipe, the intended position of a control valve.

Page 15: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

RT Entities (Details)

� An RT entity has

� Static Attributes: Name, Type, Value Domain, Max Rate of Change

� Dynamic Attributes: Value at a Particular instant� Dynamic Attributes: Value at a Particular instant

Observation:

The information about the state of an RT entity at a particular instant is captured by the notion of an observation.

atomic data structure:

Observation = <Name, Value, tobs >

Page 16: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Putting it all together!

� At the Communcation Network Interface (CNI) within a node, the picture of the RT entities are periodically updated by the real time communication system.

The computational tasks within the hosts of a node take these � The computational tasks within the hosts of a node take these RT entities as inputs to calculate the required outputs within an a priori-known worst case execution time.

� The outputs of the host are stored in the CNI and transported by the TT communication system to the CNIs of other nodes at a priori-determined instants.

Page 17: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Time-Triggered Model

Page 18: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

State Information vs Event Information

� State Observation:

� <Name of variable, value , time of observation>

� Event (Sudden change of the state of an RT entity) Observation:� Event (Sudden change of the state of an RT entity) Observation:

� <Name of variable, value difference, time of event>

� Two alternative approaches for the information that is exchanged across interfaces:

� Periodic State Observation

� Sporadic Event Observation

Page 19: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Let’s Concentrate on Communication System

� Communication system is autonomous.

� Executes periodically an a priori-specified Time Division Multiple Access (TDMA) schedule

� It reads a message from the CNI at the sending node at the a priori-known fetch instant and delivers it to the CNIs of all other nodes of the cluster at the a priori-known delivery instant, replacing the previous version of the message.

� These a-priori times are held in the Message Descriptor List (MEDL)

Page 20: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Interconnection Topology(TTA-Bus)

Page 21: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Guardians� Guardians are independent units that monitor the known

temporal behavior of the associated node.

� If a node intends to send a message outside it’s a priori-determined time slot, the guardian will cut off the physical determined time slot, the guardian will cut off the physical transmission path and thus, eliminate this failure mode.

� But what if the Guardian fails itself?

� Ideally the Guardians must be completely independent units with their:

� own clock

� power supply

� distributed clock synchronization algorithms

� indepdendent chip packages (Expensive!)

Page 22: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Interconnection Topology(TTA-Star)

Page 23: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Advantage of TTA-Star Topology

� Guardians are fully independent and located at a physical distance from the nodes they are to protect

� Less indepdendent chip packages are needed (Less cost)

� Algorithms in the guardians can be extended to provide additional services

Page 24: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Agenda

� Introduction

� Time Triggered Architecture’s Detail

� Principles that Guided the Design of TTA

� Communication Infrastructure of the TTA� Communication Infrastructure of the TTA

TTP/C protocol

TTP/A Protocol

� TTA Design Methodology

� Conclusion

Page 25: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Consistent Distributed Computing Base

� Main purpose of TTA is to provide a CONSISTENT distributed computing base to all CORRECT nodes in order that RELIABLE DISTRIBUTED APPLICATIONS can be built with manageable effort.

� Two main advantages of TTA:

� Easy to extract global state (Easy to develop algortihms)

� Immediate Error Detection

Page 26: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Temporal Predictability & Temporal Firewall

Page 27: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Temporal Predictability & Temporal

Firewall

� Result of Push- Pull architecture:

� A receiver that is working on a time critical task is never interrupted by a control signal from the communication system

� Good News

� Temporal Predictability

� No propagation of a control error through an interface (Temporal Firewall)

Page 28: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Composability

� Four Principles of Composability

� Independent Development of Nodes

� Stability of Prior Services

� Nodes must provide intended services across the well-� Nodes must provide intended services across the well-specified node interfaces

� Constructive integration of Nodes

� Replica Determinism

� All nodes have the same externally visible state

� Produce the same output messages at points in time that are at most a interval of d time units apart

Page 29: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Scalability

� TTA is intended for the design of very large distributed real time applications.

� CNIs encapsulate a function and make only those properties of the environment visible to the this encapsulated function that the environment visible to the this encapsulated function that are relevant for the correct operation of the function.

� Concept of Multiple Clusters and Gateway Nodes.

Page 30: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Joining Clusters through Gateways

Page 31: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Transparent Implementation of Fault

Tolerance

Page 32: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Openness

� Large distributed real-time systems need to be integrated into the global information infrastructure

� Efforts to standardize the interfaces of the TTA by Object Management Group (OMG)

� This will allow any CORBA-compliant client to access the internal data of TTA

Page 33: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Agenda

� Introduction

� Time Triggered Architecture’s Detail

� Principles that Guided the Design of TTA

� Communication Infrastructure of the TTA� Communication Infrastructure of the TTA

TTP/C protocol

TTP/A Protocol

� TTA Design Methodology

� Conclusion

Page 34: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

The TTP/C Protocol

� Provides the following services:

� Autonomous and Fault-Tolerant message transport with known delay and bounded jitter between the CNIs of the nodes of a cluster by employing a TDMA strategy

� Fault-tolerant clock synchronization

� Membership service to inform every node consistently about the “health state” of every other node of the cluster

Page 35: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Details of TTP/C

� Communication is organized into rounds, where every node must send a message in every round.

� A particular message may carry upto 240 bytes of data. The data is protected by a 24-bit CRC checksum.data is protected by a 24-bit CRC checksum.

� To achieve high data efficiency the sender name and the message name is derived from the send instant

Page 36: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Details of TTP/C

� The clock synchronization of TTP/C exploits the common knowledge of the send schedule.

� Every node measures the difference between the a priori known expected and the actually observed arrival time of a correct message to learn about the difference between the sender’s message to learn about the difference between the sender’s clock and the receiver’s clock.

� This information is used by an algorithm to calculate periodically a correction term for the local clock in order to keep the clock in synchrony with all other clocks of the cluster.

Page 37: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

TTP/A Protocol

� Used to connect low cost smart transducers to a node of the TTA, which acts as the master of a transducer cluster.

� There is an Interface File System (IFS) in the smart transducer.

� The information between the IFS of the smart transducer and the CNI of the TTA node is exchanged by the TTP/A protocol

� The TTP/A protocol also supports a “plug n play” mode where new sensors are detected, configured and integrated into a running system online and dynamically.

Page 38: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Agenda

� Introduction

� Time Triggered Architecture’s Detail

� Principles that Guided the Design of TTA

� Communication Infrastructure of the TTA� Communication Infrastructure of the TTA

TTP/C protocol

TTP/A Protocol

� TTA Design Methodology

� Conclusion

Page 39: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

TTA Design Methodology

� A) Architecture Design

� B) Node Design� B) Node Design

� C) Validation

Page 40: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Architecture Design

� In this phase, an application is decomposed into clusters and nodes.

� After the decomposition has been completed, the CNIs of the node must be specified in the temporal and in the value domainnode must be specified in the temporal and in the value domain

� At the end of the architecture design phase, the precise interface specification of the nodes are available.

� Theses interface specifications of the nodes are the inputs and constraints of the node design.

Page 41: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Node Design

� During the node design phase, the application software for the host computer is developed.

� The delivery and fetch instants established during the architecture design phase are the precondition and architecture design phase are the precondition and postconditions for the temporal validation of the application software.

Page 42: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Validation

� Today, the integration and validation phases are probably the most expensive phases in the implementation of a large distributed real time system.

TTA’s characteristics reduce the integration and validation effort.� TTA’s characteristics reduce the integration and validation effort.

Page 43: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Conclusion

� TTA design methodology is currently supported by a comprehensive set of design tools from a company named, TTTech.

In the domain of Distributed Control Systems, there is interest � In the domain of Distributed Control Systems, there is interest in this architecture because of strict temporal accuracy requirements.

Page 44: THE TIME-TRIGGERED ARCHITECTUREblough.ece.gatech.edu/6102/presentations/tariq_virani.pdf · 2009-04-24 · A framework for the design of a class of computing system that share a common

Thank you!