Tanner EDA Tools v16.3 Release Notes (Japanese)

7/24/2019 Tanner EDA Tools v16.3 Release Notes (Japanese)

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FAR 48 CFR 12.212

DFARS 48 CFR 227.7202

www.mentor.com/trademarks.

LinuxLMILMI

www.mentor.com/eula

Mentor Graphics Corporation

8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777

Telephone: 503.685.7000

Toll-Free Telephone: 800.592.2210

Website:www.mentorg.co.jp/

SupportNet:https://supportnet.mentor.com

supportnet.mentor.com/user_jp/feedback_form
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Tanner EDA Tools Version 16.31 .......................................................................................... 5

S-Edit v16.31 ...................................................................................................................................................... 5T-Spice v16.31 ..................................................................................................................................................... 6W-Edit v16.31 ...................................................................................................................................................... 6

L-Edit v16.31 ........................................................................................................................................................ 6HiPer Verify v16.31 .............................................................................................................................................. 6Tanner EDA Tools Version 16.30 .......................................................................................... 7

S-Edit v16.30 ...................................................................................................................................................... 7T-Spice v16.30 ................................................................................................................................................... 8W-Edit v16.30 .................................................................................................................................................. 10L-Edit v16.30 .................................................................................................................................................... 11HiPer Verify v16.30 .......................................................................................................................................... 16HiPer PX v16.30 ............................................................................................................................................... 16 ................................................................................................................................................................ 16

Tanner Tools Version 16.25 ................................................................................................ 17S-Edit v16.25 .................................................................................................................................................... 17T-Spice v16.25 ................................................................................................................................................. 17W-Edit v16.25 .................................................................................................................................................. 17L-Edit v16.25 .................................................................................................................................................... 17HiPer Verify v16.25 .......................................................................................................................................... 17HiPer PX v16.25 ............................................................................................................................................... 17

Tanner EDA Tools Version 16.24 ........................................................................................ 18S-Edit v16.24 .................................................................................................................................................... 18T-Spice v16.24 ................................................................................................................................................. 18W-Edit v16.24 .................................................................................................................................................. 18L-Edit v16.24 .................................................................................................................................................... 18HiPer Verify v16.24 .......................................................................................................................................... 18

Tanner EDA Tools Version 16.23 ........................................................................................ 19S-Edit v16.23 .................................................................................................................................................... 19T-Spice v16.23 ................................................................................................................................................. 19W-Edit v16.23 .................................................................................................................................................. 19L-Edit v16.23 .................................................................................................................................................... 19HiPer Verify v16.23 .......................................................................................................................................... 20Tanner EDA Tools v16.23 ...................................................................................................... 21Linux Tanner EDA Tools v16.23 ................................................................................................................ 21

Tanner EDA Tools Version 16.22 ........................................................................................ 22S-Edit v16.22 .................................................................................................................................................... 22T-Spice v16.22 ................................................................................................................................................. 22W-Edit v16.22 .................................................................................................................................................. 22L-Edit v16.22 .................................................................................................................................................... 22HiPer Verify v16.22 .......................................................................................................................................... 23Linux v16.22 ................................................................................................................................................. 23

Tanner EDA Tools Version 16.21 ........................................................................................ 24S-Edit v16.21 .................................................................................................................................................... 24T-Spice v16.21 ................................................................................................................................................. 24W-Edit v16.21 .................................................................................................................................................. 24L-Edit v16.21 .................................................................................................................................................... 24HiPer Verify v16.21 .......................................................................................................................................... 25Linux v16.21 ................................................................................................................................................. 25



Tanner EDA Tools Linux v16.12 ................................................................................................................ 31Tanner EDA Tools Version 16.11 ........................................................................................ 32


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S-Edit v16.11 .................................................................................................................................................... 32T-Spice v16.11 ................................................................................................................................................. 32W-Edit v16.11 .................................................................................................................................................. 32L-Edit v16.11 .................................................................................................................................................... 32HiPer Verify v16.11 .......................................................................................................................................... 32Tanner EDA Tools v16.11 ................................................................................................................................ 33


Tanner EDA Tools Version 16.04 ........................................................................................ 43S-Edit v16.04 .................................................................................................................................................... 43T-Spice v16.04 ................................................................................................................................................. 43W-Edit v16.04 .................................................................................................................................................. 43L-Edit v16.04 .................................................................................................................................................... 43HiPer Verify v16.04 .......................................................................................................................................... 44Tanner EDA Tools Linux v16.04 ................................................................................................................ 44

Tanner EDA Tools Version 16.03 ........................................................................................ 45S-Edit v16.03 .................................................................................................................................................... 45

T-Spice v16.03 ................................................................................................................................................. 45W-Edit v16.03 .................................................................................................................................................. 45L-Edit v16.03 .................................................................................................................................................... 46HiPer Verify v16.03 .......................................................................................................................................... 47


Tanner EDA Tools Version 16.01 ........................................................................................ 50S-Edit v16.01 .................................................................................................................................................... 50T-Spice v16.01 ................................................................................................................................................. 50W-Edit v16.01 .................................................................................................................................................. 51

L-Edit v16.01 .................................................................................................................................................... 51HiPer Verify v16.01 .......................................................................................................................................... 53HiPer PX v16.01 ............................................................................................................................................... 53

Tanner EDA Tools Version 16.00 ........................................................................................ 54S-Edit v16.00 .................................................................................................................................................... 54T-Spice v16.00 ................................................................................................................................................. 55W-Edit v16.00 .................................................................................................................................................. 56L-Edit Pro v16.00 ............................................................................................................................................. 59HiPer Verify v16.00 .......................................................................................................................................... 65

...................................................................................................................... 67 ..................................................................................................................................... 67 ........................................................................................................................................................ 67 ................................................................................................................................................................ 67 ........................................................................................................................................................ 68

OpenAccess .................................................................................................................................................................. 68 ................................................................................................................................................................... 68

............................................................................................................ 68


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Tanner EDA Tools Version 16.31

S-Edit v16.31

Verilog-A

T-Spice

Small Signal Parameters

SPICE -nodesigncheck SPICE

V16.30

EDIF

timestamp

timestamp

v16.30

ORCAD EDIF


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T-Spice v16.31

KLU linear solver failed invalid inputs

HSPICE W-Edit Wavetool

subckt sub1

: xsub3 xsub2.internalnode1 xsub2.internalnode2 sub3

W-Edit v16.31

L-Edit v16.31

L-Edit Duplicate By

Dublicate By

UPI LCell_UpdateToOpenAccess

LCell_UpdateFromOpenAccess L-Edit

OA

> > >

OA integer

16.3016.25tdb

V16.30 T-Cell

SDL

HiPer Verify v16.31


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S-Edit v16.30

annotate Annotate Param

Instance Params, Device Params, Models

Params,

S-Edit GUI

.

S-Edit

%VARIABLE% $VARIABLE ${VARIABLE}

ABC

ABC

Description

non-editable

(inherited)

SPICE.OUTPUT %vdd

S-Edit

L-Edit

CDF >>CDF

(.temp)

TCL workspace menu

S-Edit

GUIworkspace menu -help

workspace menu -name {} -after (H)


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S-Edit T-Spice

S-Edit

RevisionCount 1

SPICE.OUTPUT

Spice

EDIF

Spice SDL.OUTPUT SDL

K

2

T-Spice v16.30

T-Spice


Checkpoint-restart

HiSim version 2.8

HiSIM_HVversions2.102.20 high voltage

T-Spice S-Edit

T-Spice GUI

/

Setup > Application > External Programs

> Digital simulator path Verilog-AMS

BSIM PARAMCHK 3

paramchk

0 1

Simulation > Simulation Settings | Output Empty simulation manager list


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DC

autoconv=[0|1] (default: 1)

BSIM4 DTEMP DC .IC

AMSAldec

Riviera Pro dataset.asdb Modelsim/Questa vsim.wlf T-

Spice

*.measure *.monte

T-Spice S-Edit

T-Spice GUI

MACMOD MOSFET

MEASFORM .measure

Verilog-A/MS T-Spice File > Encrypt

&& (AND) || (OR)

.

HiSIM_HV

.measure

Juncap

Juncap :AREA -> AB, PJ -> LS, PGATE -> LG.

x1

xsense x1.nodeQ senser

"no dc path to gnd" gshunt cshunt

mod_name .model

model=mod_name .assert

Simulation > Compile Verilog-AMS

.assert duration=d d

Philips/NXP Juncap type -

1 1

.subckt .print


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i(instance_name, pin_name)

.print i(xtop.xinverter,out)

Wavetool HSPICE

NXP/Philips (Mextram, Diode500, ) Windows 64 bit

node=name .assert

W-Edit v16.30

measure pp

Y Y

Absolute jitter begin

Raw littel/big endian byte order


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L-Edit v16.30

GUI

L-Edit GUI Japanese

PyCells

L-Edit PyCell (iPDK)

iPDK

Python

Python PyCell PyCell

Windows 64-bit L-Edit

T-Cell

T-Cell Radio

T-Cell

UseQuery Editable

Use Query

TCL Editable

TCL

T-Cell

TCL

OpenAccess tcl OpenAccess

autoload.tanner TCL

autoload.tanner

autoload.file

autoload.tanner autoload.file

L-Edit

"C:Program FilesTanner EDATanner Tools v16.2ledit64.exe" -t

"C:TannerMyLeditProcedures.tcl"

One by one..

One by one..

Highlight

i) ii) iii)

Find in Hierarchy


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i) ii) iii)

iv)

1

Highlight

i) ii) iii)

Automatic Viewport Change >

| i) ii)

iii)

S-Edit

Options

XY

> | Grid XY

XY

Retarget library

of selected cells...

i) ii)

iii) iv)

OpenAccess

> > General

OpenAccess

OpenAccess

No Cells,

,

PDK

PDK

OpenAccess

Toplevel In Use in File


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SDL

SDL

> > TechLayers Pitch Offset

SDL Setup Router

SDL

> > Tech Layers

.

SDL "Insert multiple devices where M>1"

"Remove device designator"

SDL

C, R, D L CP/CM, RP/RM, DP/DM,

LP/LM PLUS/MINUS

PLUS/MINUS

PDK

SDL

SPEF

HiPer PX Standard Parasitic Exchange Format (SPEF)

SDL SDL

> SPEFPX

F1 pdf

Adobe Reader

Foxit PDF Reader

Calibre

Calibre Interactive Calibre

Calibre L-Edit

Tanner EDA EVICalibre RVE GUI EVI DRC, LVS, PX L-Edit

S-Edit

L-Edit OpenAccess

Confirm Toplevel Library

L-Edit



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> > Instance

Name

> Reorder

drop-down

SDL

Highlight Layout

SDL

SDL

Highlight Net 'XXX' SDL

UPI LSelection_ConvertToCurvedPolygon ()

> | General

DXFGerber UPI

LFile_ImportDXF, LCell_ExportDXF LFile_ImportGerberFolder, LFile_ImportGerberFile, LCell_ExportGerber,LCell_ExportGerberDrill

LCell_GetParameterAsTime() UPI

UPI LFile_ImportTechnology_GDSLayerMap GDS Layer

Map

UPI LFile_ImportTechnology_LEF import LEF Technology

OA

name aliase

TCL workspace menu

workspace menu -help

workspace menu -name {View Testme } -command { puts "test1" }

DRC

L-Edit

Edit Object Delta

T-Cell divide by zero

Cell Copy

Cell

Copy

SDL autogen T-Cell

autogen


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Delete layer even if it contains geometry

L-Edit &

>

"X Y corner and

dimensions"

.

DXF

TDB T-Cell

Highlight Node

DXF Gerber

Customize... Import/Export Mask Data

DXFGerber

> / display unit technology unit

Results Database Verification Error Navigator Center

view on error & zoom "CN"

OASIS

SDL

SDL LEF TDB

Alt+M

OpenAccess

OpenAccess UPI

Paste to Cursor

> > DRC, ,

DRC

OpenAccess

TDB


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>

OpenAccess

L-Edit

Oasis

TDB

OpenAccess Blockage Boundary

HiPer Verify v16.30

HiPer Verify

%VARIABLE% $VARIABLE

Verification Error Navigator

DRC

Verification Error Navigator

Calibre RVE

Extract Device

LVS

HiPer PX v16.30

SDLSPEF

HiPer PX Standard Parasitic Exchange Format (SPEF)

SDL SDL

> SPEFPX

HiPer PX %VARIABLE% $VARIABLE

Setup DRC Calibre Define HiPer

PX L-Edit

16.30 Tanner EDA Microsoft Windows XP, Vista

RedHat 4

Windows 7, Windows 8, Windows 8.1, RedHat 5

RedHat 6


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Tanner Tools Version 16.25

S-Edit v16.25 S-Edit v16.25

T-Spice v16.25 Philips/NXP Juncap TYPE

-1 1

W-Edit v16.25 W-Edit v16.25

L-Edit v16.25

OpenAccess

HiPer Verify v16.25 HiPer Verify v16.25

HiPer PX v16.25


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S-Edit v16.24

T-Spice v16.24

VA (* desc="VDSAT" *) real VDSAT; Verilog-A

.alter *.monte

.alter

.option modmonte

M multiplicity

/* comment */ */

Verilog-A `include


L-Edit v16.24

Clear Layer

CIF

HiPer Verify v16.24 DRC TOLERANCE FACTOR

0.001u DRC

EXT, ENC, INT REGION


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S-Edit v16.23

T-Spice v16.23

Spice

.print

AC mout M

HiSIM_HV (.option probeq)

Bad Getparam() call

BSIM-SOI version 3.2 flicker

VHDL v16.22

HiSIM_HV 1.242.01 HiSIM 2.61


L-Edit v16.23

SDL

L-Edit

OA >|General

Paste to cursorL-Edit


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T-Cell LCell_MakeLogo L-Edit

> TDB

OA

/ Result

LEF obstruction

SDL

> | UPI Update display

> (M)

T-Cell divide by zero

L-Edit

OA > TDB

T-Cell "true" T

F

(Undo) T-Cell

L-Edit S-Edit

L-Edit

LObject_ChangeLayer LSelection_ChangeLayer UPI

>Add-Ins > OA

HiPer Verify v16.23 / "Open SPICE output

file after extracting"

LVS X

PX Netlist extraction fails because of an unknown

reason

Edge INT Netlist extraction fails because

of an unknown reason

edge Dimensional Check Operations


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Tanner EDA Tools v16.23

W-Edit

Win XP 32bitSupport Utilities

Linux Tanner EDA Tools v16.23

LVS "No relevant top-level

circuitry to flatten"


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S-Edit v16.22

tcl database instances, ports, labels, netlabels netcaps

-selected database instances -selected

>>Spice

T-Spice v16.22

Verilog-A $strobe

preview

Verilog-A

Verilog-A

"Verilog-A license failure"

AC HiSIM_HV MOSFET

(:) .measure .print

.print tran ddt(i2(Xosc)) ; .measure tran I2_Avg avg

i2(Xinverter)

W-Edit v16.22

W-Edit v16.22

L-Edit v16.22

> SDL > LEF/DEF L-Edit

> >

L-Edit

T-Cell Cell Information

T-Cell Delete


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Move perpendicularly

SDL

OpenAccess Spice extract output

Tdb 256

L-Edit

SDL (HiPer SPR)

Tdb > "File

Information"

:

L-Comp LC_InitializeState()

L-Comp

LC_InitializeState

LC_InitializeStateFromCell(cellCurrent) L-Edit

T-Cell

LC_InitializeState

HiPer Verify v16.22

DENSITY NET AREA RATIO RDB

Linux v16.22

Linux v16.22


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S-Edit v16.21

True,False

Expression Expression

tcl

[ MyExpr TestPar]

T-Spice v16.21

W-Edit v16.21

W-Edit v16.21

L-Edit v16.21

45

x delta y delta 90GDSII

Save All

TDB

L-Edit

OA L-Edit L-Edit

LVL

OA L-Edit L-Edit


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HiPer Verify v16.21

RDB (Results Database)

RDB

Linux v16.21

W-Edit


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S-Edit v16.20

S-Edit

Layout

L-Edit Layout

L-Edit

S-Edit Publish to SDL S-Edit SDL

L-Edit SDL

SDL SPICE

S-Edit

Query

Query True

Show Query Query True

False

Editable

v16.20 Cadence

.cdsParam

IPL

S-Edit v16.20 IPL

S-Edit tcl

setup schematictext set -stretch

S-Edit

%appdata%Tanner EDAscriptsstartup

S-Edit tcl

setup schematictext set fontface

S-Edit %appdata%Tanner EDAscriptsstartup


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transient, dc, ac and parameter sweeps

"Data"

LibraryName_unresolved

> > Spice m

> veriloga verilogams

270

T-Spice v16.20

Simulation Status

transient ramp powerup

T_ABS (absolute

temperature)

. warcommand Verilog-A/MS

.IC

.noise listcount=n

binned modelname.1,Philips

MOS 11 PSP

.temp to tnom

.IC .nodeset

W/L

RPI a-Si Level 15 TFT

dtemp delta

ID undefined total noise

Verilog-A

W-Edit v16.20

"measure fft"

DC

"-dcremove 1" "dcremove"


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L-Edit v16.20

L-Edit

S-Edit

S-Edit

SDL Assisted Routing

SDL

SDL

SDL

*

DRC

SDL SDL >

S-Edit Publish to SDL

S-Edit SDL

L-Edit SDL

>

OASIS"Type 0"

SDL >

SDL >


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GDS "begin struct" "end struct"

>

Shift+]

SDL

L-Edit

MultiGrid

Match whole names only

TCL layer datatype

Layout Text Generator

L-Edit

Copy/Add Layer Mask Bias

GDS TDB I/O

L-Edit Circle, Pie, Torus

LFile_SaveAs OA

HiPer Verify v16.20

DRC/Extract

HiPer Verify LVS PROPERTY INITIALIZE

LVS

LVS LVS

LVS prematch

LVS

L-Edit>

HiPer VerifyL-Edit

Windows XP Tanner EDA Tools v16.2


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S-Edit v16.12

OpenAccess SimInfo export

"symbol"

SPICE

T-Spice v16.12

ddt() invalid 0

(if(c,a,b) c?a:b)

limit(value, min_value, max_value)

IS diode expli

dc tran .measure

W-Edit v16.12 W-Edit

L-Edit v16.12

V16.10

OASIS

Locked Mirror

2


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HiPer Verify v16.12

LVS

Tanner EDA Tools Linux v16.12

S-Edit, L-Edit W-Edit GUI


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S-Edit v16.11

Verilog "end" "endcase"

OpenAccess "radio"

T-Spice v16.11

AC

V16.10.subckt

(gnd, gnd!, ground, .global node)

W-Edit v16.11

GUI

Shift+&

L-Edit v16.11

SDL

HiPer Verify v16.11

LVS -1 -2

Verilog


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Tanner EDA Tools v16.11

tcl8 tcl


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S-Edit v16.10

OpenAccess

OpenAccess S-Edit

S-Edit

Cadence OpenAccess cdfDump

Cadence cdsParam

S-Edit L-Edit

S-Edit L-Edit

S-Edit

L-Edit S-Edit L-Edit >

L-Edit

SDL

PDF

S-Edit Enhanced Metafile

Metafile

S-Edit >

TCL

F6

tcl "workspace bindkeys"

tcl

"workspace" "toolbar""bindkeys""dockinglayout"

tcl "workspace getactive"

S-Edit X MEG

VERILOG.PRIMITIVE = True Verilog

Copy Cell


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Copy Cell Overwrite

Save modified Libraries

"Pages" "PageNumber"

W-Edit "Unknown term"

SPICE

SPICE

verilog/spice

verilog/spice

T-Spice v16.10

DC/Parameter

param DC

.DC Vin 2 4 0.1 .param Vin=3v

Juncap BSIM3 v3.3 BSIM4 v4.7 bulk-

drain bulk-source

.model juncap=2 (0 = use native BSIM

diodes, 1 = Juncap 1 diodes, 2 = Juncap 2 diodes, default value: 0).

Juncap BSIM .model

.subckt

Verilog-A/MS

.option Vadatabase = FolderPath

i1(x1.xcontroller)

.warn

Verilog-A

R2_CMC R3_CMC , HICUM bipolars, BSIM6 BSIM-CMG

MOSFETs Verilog-A

AC transit-time knee-current

BSIM SASBSD

stress effect

g e VCCS VCVS

cur='-i1(e1)'

.data

alter (.del lib my.lib typical)

(.lib my.lib typical)


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MOS SA, SB SD

.assert level=notice

mod=name .assert

.ic

.nodeset

.option tolmult

.title (.alter=0)

.op .tran BSIM4

time=0

alter .assert when=setup .step .dc

data .alter .param

.param .alter

.step

.temp .param

.measure .step .DC

.step

.dc .tran

Verilog-A "$fopen("filename.txt", "a");"

"$fopen("filename.txt");"


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L-Edit v16.10

SDL

SDL

SpiceCDL Verilog LEF

SDL LEF/DEF

SDL

tdb

> "Tech Layers" routing

pin keep out

SDL

SDL SDF Standard Delay Format

SDL Extract > Write

SDF

Verilog SDL

SDL LEF DEF

SDL

SDL (SDL

>> )SDL

OASIS

L-Edit OASIS /

> "Locked"

L-Edit

> |

Selection

L-Edit

Themes (Windows > Theme)

v16.10

v16.10


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GDS

File > Open

GDS GDS L-Edit

Cell Copy

GDS OA

L-Edit

255GDS Datatype

overlapping unpinned docking views

overlapping unpinned docking views

Windows > Themes

>

> (M)

Draw > Layout Generators > Layout Text Generator

UPI LCell_MakeLogo

Gerber

(RS274X )

> Filter by Net

SDL

SDL Router SDL Check connectivity

library:cell*view

TCL

Customize | Commands

Custom Execute button text as Tcl "workspace userbutton"

TCL

TCL "workspace toolbar"

"workspace userbutton"

"workspace" "toolbar", "bindkeys" "dockinglayout"

>"Fracture Polygons"


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Libraries Navigator

SDL

Cadence Allegro Gerber

SDL "By Instance"

GDS

Round Join End style Object Snapping L-Edit

Round end/join

Generate Layers Boolean Operations DRC Extract 8190

"[" "]"

SPR EDIF "There was no TDB standard cell

library selected"

Unresolved autogen "X"

T-Cell "X"

OA Unreserve Save

OA

SDL Router

v15 stdVias custom via

'tech.tdb.cdslck' L-

Edit

Clear Markers

GDS

layer-purpose-pair

Copy Hierarchy

>

"Consider multiple edges as single edge" "Only consider

vertices whose angle is"

> >

UPI

Die labeler


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Clear markers

surround

CIF

HiPer Verify v16.10

HiPer PX HiPer Verify Extract

HiPer Verify HiPer Verify

HiPer PX L-Edit

> Add-Ins >

Legacy Parasitic Extractor

LVS

LVS LVS

Unicode

LVS Structural Verilog

LVS

Parasitics

Remove device models named:"

LVS S-Edit

L-Edit

DRC

DRC Calibre

Dracula Tanner XML

(*.tdr) Calibre Dracula

Tanner XML

GDSII

BY NET CUT ENCLOSE INTERACT TOUCH

EVEN/ODD CUT TOUCH ENCLOSE INTERACT

SINGULAR ALSO SINGULAR ONLY INTERACT

REGION CENTERLINE dimensional check

ANGLE

CORNER TO CORNER


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ENCLOSE

RECTANGLES INSIDE OF

INT EXT ENC ABUT

INT EXT

ENC

SINGULAR

INT EXT ENC

ENC OUTSIDE ALSO

EXT PERP

dimensional check >a < b

RECTANGLE ENCLOSURE SINGULAR

connect NET AREA RATIO BY layer

NET AREA RATIO

SCONNECT BY BY layer

OpenAccess HiPer Verify

GDS Layer-Purpose-pairs

OpenAccess

OFFGRID PRECISION TDB

Dimensional INTEXTENCimplicit

Scale factor

Save node highlight data

DRC Setup Extract Setup Define


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S-Edit v16.04

VHDL

Spice

T-Spice v16.04

Transit Time (TT) Knee Current

(IK IKR)

AC

.ic .nodeset

q=

HSPICE Bveff

BV 10*Vt

Mextram

W-Edit v16.04 WMF

PNG

WMF PNG

"chart image -format "

L-Edit v16.04

Delta 0DRC

L-Edit

OA GDS

L-Edit

Verilog SDL


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SDL

Gerber window trace

>

OA

L-Edit

"A" "Label Layer -- Tanner

internal system layer"

L-Edit DrgEnbl

Virtuoso Cadence OA

L-Edit L-Edit

rotate

3>

Hide Instances and Hide Objects "Show

maximum detail" Options

HiPer Verify v16.04 HiPer Verify v16.04

Tanner EDA Tools Linux v16.04 S-Edit

home .wine-

tanner


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S-Edit v16.03

(Ctrl+D)

>

: :

SPICE >

Verilog

Verilog Spice

Verilog Spice

Verilog

S-Edit v16$Cell v15 $Cell

$Model

SPICE

v15

$Cell ${cell} $MasterCell

.

Spice Verilog

T-Spice v16.03

HiSIM_HV AC

S-Edit / T-Spice

BV IK sqrt

DC OP

stepping

expli

W-Edit v16.03


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L-Edit v16.03

"False cycle in hierarchy"

OA DRC

DRC

PDK autogen

OpenAccess delay read T-Cell

"On Layer"

T-Cell

Virtuoso drawing purpose custom

purpose

> Show box coordinates using

"Top left corner and dimensions" "Top right corner and

dimensions" "Bottom right corner and dimensions"

Virtuoso lxMPPTemplates

autogen

LCell_GetLock v15

LCell_ClearGenerateLayers

v15

LMacro_LoadEx1200

LDisplay_Refresh()

AA AA

v16.0 PDK T-Cell v15

v16 T-Cell dll

v16 L-Edit .tdb dll

"help" Tcl "help"

Tcl "help "

"help all"

S-Edit/W-Edit

TDB Virtuoso

> > Valid vias


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ALT+RMB

L-Edit

OA invalid layer

>

Import Results

Tools > Add-Ins > LoadCalibre DRC Results Database Calibre

DRC

OA T-Cell

HiPer Verify v16.03

DRC Extraction L-Edit

HiPer Verify

LVS .param

LDisplay_Refresh()


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S-Edit v16.02

Spice

T-Spice v16.02

Verilog-A

"Simulation file can't be opened for writing"

param

".options monteinfo=2"

"T-Spice v16.0 Model Documentation" PDF

W-Edit v16.02

/ >

stacked

> Move Curves > Move Curves Up/Down


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L-Edit v16.02

L-Edit

Ctrl+S Ctrl+W

DXF

Gerber

tdb

L-Edit auto gen T-Cell dll

auto gen

Lcomp T-Cell

UPI_Entry_Point

DRC

"Show All Layers and Start"

"Include objects on hidden layers?" "Ask

every time"

Warning

Gerber Gerber

GDS

OpenAccess

HiPer Verify v16.02

CMACRO

DENSITY AREA()

RECTANGLES

SHIFT

Extract

"Rules with Errors" SCONNECT

Verification Error "DRC " "

"


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S-Edit v16.01

"undo clear"

"redo clear" TCL

"design save all" TCL

undo

"Save" procedure

Add back-annotation for ports

SPICE

SPICE.ENDDEFINITION ".ends"

Ctrl+S

S-Edit

Spice

10

Spice

Verilog Verilog

EDIF Cadence

T-Spice v16.01

S-Edit T-Spice T-Spice

Verilog-AMS

T-Spice

TANNER_ALDEC_DIR GUI Simulation settings > Verilog-

AMS > Aldec Installation

Riviera Pro


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( c:) .lib

.include

BIT Delay

scale bin

MOS model 20

MOS model 30

.dellib .alter

PWL

T-Spice Simulation Setting Aldec

W-Edit v16.01

CTRL-UP

() CTRL-DOWN v16.00

SHIFT+UP

SHIFT+DOWN

L-Edit v16.01

Tools >

Measure > Between Selections

Page Up/ Page Down

Tools > Measure > Set MeasurementReference

Tools > Measure > To

Current Selection

>


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UPI

V16 GDS

GDS LFile_Open

V16GDS UPI

LFile_ImportGDSII CIF

LFile_ImportCIF

tdb

/

Partly Enclosed

Alt +

(implicit edge selection)

Edit-In-Place

>>Selection Selection range 0

>>SelectionEdit range

Edit-In-Place

Edit Object Edit Object

/

45

Perpendicular Edge Move

45

Ctrl+R 90


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"current layer"

T-Cell

T-Cell

>

DXF GDSII

DXF

DXF

DXF b-spline

SDLVerilog

T-Cell OA

Layer

(OA)

(OA)

HiPer Verify v16.01 64bitPC Tanner EDA Tools 32bit

HiPer Verify Node Highlighting

64bit Windows L-

Edit 32bit 64bitleditdrc

32bit

DRC

//

DRC

HiPer PX v16.01 45 HiPer PX


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S-Edit v16.00

Verilog Verilog-AMS

Verilog-AMS S-Edit

Verilog Verilog-AMS verilog

RTL Structural Verilog (netlists) Verilog-AMS

Verilog-A Verilog-D

schematic, spice, Verilog

>

veriloga

Verilog

veriloga

verilog

Spice Verilog .subckt /module

EDIF

Verilog

Spice

Replace

S-Edit

"missing cell"


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DC S-Edit

SPICE

Spice '@'

V15

T-Spice v16.00

T-Spice Aldec

Riviera Pro Mentor ModelSim Verilog-AMS

HiSIM2 HiSIM_HV

Berkeley BSIM Philips

Tunnel Saturation T-Spice

BSIM3 BSIM4 MOSFET delvto

mulu0

NXP/Philips (MOS 9, PSP, Mestram, Juncap, )

.print device:state

T-Spice GUI Simulation > Batch Simulations

.options

maxsyntaxerror=n (default n=5)

Verilog-AMS 132

T-Spice

.hdl Verilog-AMS

vasearch search


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.subckt .global

Verilog-A .subckt .model

PSP

swgeo

"Unsupported model level 69"

.assert start stop

.print

(cscaled * 5)

BJT

External C Models C

Verilog-A

W-Edit v16.00

x-

W-Edit

RMS

> >

Stacked


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CTRL- CTRL-

XY

>

>

Find Next Edge Find Previous Edge

x-y

>

>

gainmargin phasemargin


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"-versus" ...

measure

"-versus"

>Min, Max

AC AC >

>

DC

v15'DC/Parametric' 'X-Y'

Tanner EDA Tools v16.00 Tcl 8.5.10


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L-Edit Pro v16.00

OpenAccess

L-Edit v16 Tanner TDB OpenAccess

OpenAccess

PDK OpenAccess

OpenAccess TDB

OpenAccess

TDB

OpenAccess

ReserveUnreserve

Update Cell

Update All

L-Edit Database

Toggle edit lock, Save Cell, Save all cells, Update cell, Update all

L-Edit CAD

OpenAccess CAD Attach Reference

OpenAccess TDB Virtuoso

TDB

L-Edit Virtuoso TechnologyDisplay

L-Edit

S-Edit

L-Edit

"Valid"


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All

L-Edit OpenAccess Standard Vias Custom Vias

Valid Vias

[ ]

L-Edit

>

T-Cells

Copy Cell

i) ii) iii)

iv) v)

GDSII Data Type


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Via

GDS

GDS 6

i) ii) iii)

iv) v) vi)

GDS Export

GDS

GDS

GDS GDS number6

GDS Export UPI GDS

GDS XRefLib v16

UI

SDL

> >

OpenAccess

OpenAccess

SPR

SPR

AutoGenT-Cell _Auto#

#

SDL"Highlight Layout" Generate Layers


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LVL OA

TDB TDB OA OA OATDB

Autogen

TDB OA

TDB OpenAccess >

> OpenAccess Save TDB to OpenAccess

4

i) Local (tdb OA

)

ii) Attached OA

iii) ReferencedOA

iv) Copied OA

T-Cell T-Cell autogens

32820 T-Cell Generator cells are no longer written when exporting to GDS.These cells are allows empty, as the actual geometry is contained in the autogencells.

T-Cell Generator GDS

autogen

DRC

TDB

L-Edit

Object Snapping

Interactive DRC Shift

] [

Shift 7

]

]

>

>


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>> /

"Unrecoverable error"

> >

HiPer DevGen MOSFET Gate Bulk

SDL DP DN DP DM

T-Cell "invalid conversion from 'int' to

'LWireConfigBits'"

T-Cell T-Cell

LUpi_SetReturnCode(1) return L-Edit T-Cell

AutoGen

T-Cell dll Dll 1


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L-Edit v16 L-Edit

v16v15 L-Edit v16v16

*.backup.tdb

UPI

UPI LCell_GetName

LCell_GetFullName,LCell_GetCellName, LCell_GetViewName, LCell_GetLibName,LCell_GetPresentationName, LCell_GetCanonicalName.

L-Edit v16

UPI

T-Cell

Xref

L-Edit v15

L-Edit v16

v15 v16

v15 > XrefCells ...

Unlink

v16

TDB OpenAccess

OpenAccess TDB

OpenAccess

OpenAccess

TDB OpenAccess

TDB

TDB

L-Edit v15.x

L-Edit v16

v15.x

L-Edit v16 v15 tdb v15.x

v15.x L-Edit


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L-Edit v15 v16

v15v16

v16v15tdb viadefs

Via Layer, Lower Layer, Upper Layer2Other Layer

Fracture "Contact"

stdvia viadefs Setup > Design > Vias

stdvia viadef > > Valid Vias

stdvias Customvia viadefs

Valid Vias > > Valid Vias

...

Customvia viadefs

"contact" >

> Valid Vias Customvia viadef Valid Vias

HiPer Verify v16.00

Find Rule By Name DRC

DRC

DEFINE

DEFINEs

Calibre

HiPer Verify BooleanCoincident EdgeRectangle EnclosureNet Area

Ratio

Or Edge

Touch Edge Endpoint

GROW SEQUENTIAL

Dracula

Dracula "PARAM RES" "PARAM CAP"

Calibre

SIZE INSIDE OF

SIZE

RECTANGLE ENCLOSURE


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TOUCH EDGE COIN EDGE

HiPer ENCLOSURE

ENCLOSURE

INT

ENCLOSURE RECTANGLE

DRC

DRC

SVRF MESSAGE

Standard DRC

DRC

/

HiPer

LVS

Spice LVS

LVS

LVS

LVS


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Microsoft Windows 7, Windows 8 or Windows 8.1Intel Pentium 4 SSE 1 GB RAM425 MB 100 MB

64 MB

3

Microsoft Windows 7 64-bitWindows XP 64-bit

Dual Core Intel Xeon 2.66 GHz

PC Intel Core 2 Duo 2.00 GHz 2

Tanner EDA Tools2/

RAM

4 GB RAM HiPer Verify

1 GB 100 MB

256 MB Microsoft Intellimouse1280 x1024 True Color (24)

Tanner EDA Tools Windows

Tanner EDA Tools CD CD-ROM

CD SETUP.EXE

Tanner EDA Tools

C:Program FilesTanner

EDATanner EDA Tools vXX.YDocsAdditional Japanese Documentation

Tanner EDA Tools v16

Windows Vista

"Error 1925.All Users

"

CDsetup.exe

Tanner

WindowsTanner EDA

ToolsWindows

CD

CD

T-Spice Verilog-A Custom Installation

Minimalist GNU for Windows


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OpenAccess oaFSLockD.exe

Windows

OpenAccessOpenAccess 16725

L-Edit oafslockd.exe

TCP16725 Windows

L-Edit oafslockd.exe

30

WindowsLinux16725

Tanner EDA Tools

Mentor Graphics Tanner EDA

Tools

USB

Tanner EDA Tools

Sentinel LM 7.3.0.6

.tluTanner EDA Tools

lservrc

Tanner EDA, A Mentor Graphics

Company825 South Myrtle AvenueMonrovia, CA 91016-3424, USATel: 1-877- 304-5544 (Toll Free)

1-626-471-9700Fax: 1-626-471-9800E-mail: [email protected]: www.tannereda.com

JapanMentor Graphics Japan Co. Ltd.Tanner EDA DepartmentGotenyama Trust Tower, 20F7-35, Kita-shinagawa 4-chome

TaiwanTanner Research Taiwan, Inc.6F.-8, No. 8 Ziqiang S. Road, Jhubei CityHsinchu County, 302, TaiwanTel: 886(03)-6579108

Fax: 886(03)-6579107Email: [email protected]: www.tanner.com.tw

EuropeEDA Solutions LimitedUnit A5 Segensworth Business Centre
mailto:[email protected]://www.tannereda.com/mailto:[email protected]://www.tanner.com.tw/http://www.tanner.com.tw/mailto:[email protected]://www.tannereda.com/mailto:[email protected]

Tanner EDA Tools v16.3 Release Notes (Japanese)

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Transcript of Tanner EDA Tools v16.3 Release Notes (Japanese)