Table of Contents€¦ · 4.8 Carry Look Ahead Adder In parallel adder, the carry propagation time...

Unit 4-Part 2 : Combinational Logic Circuits

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| EE &EC Department | 3130907– Analog and Digital Electronics

Table of Contents

4.1 Introduction .......................................................................................................................................3

4.1.1 Difference between Combinational and Sequential Circuit .......................................................................3

4.2 Binary Adder Logic Circuit ...................................................................................................................3

4.2.1 Half Adder ...................................................................................................................................................4

4.2.2 Full Adder ....................................................................................................................................................4

4.2.3 Comparison between Half & Full Adder .....................................................................................................5

4.3 Binary Subtractor Logic Circuit .............................................................................................................5

4.3.1 Half Subtractor ............................................................................................................................................5

4.3.2 Full Subtractor ............................................................................................................................................5

4.4 Binary Parallel Adder/Ripple Carry Adder ............................................................................................6

4.5 Binary Parallel Subtractor (2’s Complement Adder) .............................................................................6

4.6 Binary Parallel Adder/Subtractor (2’s Complement Adder) ...................................................................7

4.6.1 Advantages of Parallel Adder/Subtractor ...................................................................................................7

4.6.2 Disadvantages of Parallel Adder/Subtractor ..............................................................................................8

4.7 BCD Adder/Decimal Adder ..................................................................................................................8

4.8 Carry Look Ahead Adder ......................................................................................................................9

4.9 Magnitude Comparator ..................................................................................................................... 11

4.9.1 2 bit Magnitude Comparator ................................................................................................................... 11

4.9.2 4 bit Magnitude Comparator ................................................................................................................... 13

4.10 Encoder ............................................................................................................................................ 14

4.10.1 8 to 3 (Octal to Binary) Encoder ............................................................................................................ 14

4.10.2 Priority Encoder ..................................................................................................................................... 15

4.11 Decoder ............................................................................................................................................ 16

4.11.1 2 to 4 Decoder ....................................................................................................................................... 16

4.11.2 3 to 8 Decoder ....................................................................................................................................... 17

4.11.3 2 to 4 Decoder with Enable ................................................................................................................... 17

4.11.4 Examples of Decoder ............................................................................................................................. 18


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4.12 Multiplexer (MUX) ............................................................................................................................ 18

4.12.1 2 to 1 (2 X 1 or 2:1) Multiplexer ............................................................................................................. 19

4.12.2 4 to 1 Multiplexer .................................................................................................................................. 19

4.12.3 8 to 1 Multiplexer .................................................................................................................................. 20

4.12.4 Examples of Multiplexer ........................................................................................................................ 20

4.13 Demultiplexer (DEMUX) .................................................................................................................... 22

4.13.1 1 X 4 Demultiplexer ............................................................................................................................... 22

4.13.2 1 X 8 Demultiplexer ............................................................................................................................... 23

4.13.3 Applications of Multiplexer and Demultiplexer ..................................................................................... 23

4.14 Parity Bit Generator and Checker ...................................................................................................... 24

4.14.1 Examples of Parity Bit Generator / Checker .......................................................................................... 25

4.15 GTU Questions .................................................................................................................................. 26


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4.1 Introduction Combinational logic circuit is a circuit in which we combine the different logic gates in the

circuit such that the output of combinational circuit at any instant of time, depends only on the logic levels present at input terminals.

Some of the characteristics of combinational circuits are following − 1. The combinational circuit do not use any memory. The previous state of input does not

have any effect on the present state of the circuit. 2. A combinational circuit can have an n number of inputs and m number of outputs.

Fig.: Block Diagram of Combinational Logic Circuit

Below logic circuit are the examples of combinational logic circuit 1. Adder and Subtractor 2. Magnitude comparator 3. Encoder and Decoder 4. Multiplexer and Demultiplexer 5. Parity Checker and Generator etc.

4.1.1 Difference between Combinational and Sequential Circuit

Combinational Circuit Sequential Circuit

1. It does not contain memory elements. 1. It contains memory elements.

2. Output depends on present state of input only.

2. Output depends not only on the present inputs but also on the past history of inputs.

3. Its behaviour is described by the set of output functions.

3. Its behaviour is described by the set of next-state (memory) functions and the set of output functions.

4. Does not use Feedback path. 4. Use Feedback path.

5. Does not require clock signal. 5. Most of sequential circuit use clock signal.

6. Faster than sequential circuit. 6. Slower than combinational circuit.

7. E.g.: Adder, Subtractor, MUX, Encoders, etc. 7. E.g. Flip Flops, Registers, Counters, etc.

4.2 Binary Adder Logic Circuit

Adder is used to add binary numbers

Binary adders are of two types; 1. Half Adder: Used to add two single bit binary numbers A & B. 2. Full Adder: Used to add two single bit binary number A & B and carry bit Cin.


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4.2.1 Half Adder

A binary adder adds two binary bits. Block diagram of half adder is shown in fig.

Half

Adder

A

B

Sum (S)

Carry(C)

Inputs Outputs

Fig.: Block diagram of half adder

There are two input terminals, which are marked as A and B. Binary numbers, the sum of which has to be made are applied here.

There are two output terminals. One terminal is for sum bit S and the other is the carry bit C.

Truth table of half adder is shown below. Table: Truth table for half adder

Inputs A B

Outputs S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

From truth table we can write the expression for sum S and carry C.

For sum and carry summing up input combinations for which the output is 1.

Sum (S) = A’B + AB’ = A ⨁ B Carry (C) = AB

It is seen that the sum S can be realized by EX-OR gate and carry C can be realized by an AND gate. Such circuit is shown in Fig.

Fig.: Circuit of half adder

4.2.2 Full Adder

Full adder is made up of two half adder and OR gate.

It has three inputs and two output.

It can able to add 3 digit at a time.

Fig. shows the full adder logic circuit using half adder and OR gate.

Fig.: Block diagram of full adder

Table: Truth table for full adder

For sum and carry summing up input

combinations for which the output is 1. S = A ⨁ B ⨁ Cin

Cout = (A ⨁ B) Cin + AB

Fig.: Circuit diagram of full adder


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4.2.3 Comparison between Half & Full Adder

Half Adder Full Adder

1. Used for 2 single bit number. 1. Used for 2 single bit & 1 carry bit number.

2. One EX-OR gate and one AND gate are used. 2. Two EX-OR gates, two AND gates and 1 OR gate are used.

3. Output is the sum of two signal. 3. Output is the sum of three signal.

4. Circuit is simple. 4. Circuit is complicated.

5. There are 2 input and output terminals. 5. There are 3 input and 2 output terminals.

6. It cannot be used as full adder. 6. It can be used as half adder.

4.3 Binary Subtractor Logic Circuit

4.3.1 Half Subtractor

The subtraction of 2 binary digits also produces two outputs which are termed as difference and borrow.

The simplest possible subtraction of 2-bit binary digits consists of four possible operations, they are 0-0, 0-1, 1-0 and 1-1.

The operations 0-0, 1-0 and 1-1 produces a subtraction of 1-bit output whereas, the remaining operation 0-1 produces a 2-bit output. They are referred as difference and borrow bit.

Table: Truth table for half adder

Inputs A B

Outputs D (Diff.) B (Borrow)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Boolean eq. from truth table;

Difference (D) = A’B + AB’ = A ⨁ B Borrow (B) = A’ B

Fig.: Circuit of half subtractor

4.3.2 Full Subtractor

Full subtractor as a combinational circuit which takes three inputs and produces two outputs difference and borrow.

Table: Truth table for half adder

Inputs A B C

Outputs D (Diff.) B (Borrow)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Boolean eq. from truth table;

Difference (D) = A ⨁ B ⨁ C Borrow (B) = (A ⨁ B)’ C + A’ B

Fig.: Circuit of full subtractor


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4.4 Binary Parallel Adder/Ripple Carry Adder

A single full adder performs the addition of two one bit numbers and an input carry. But a Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary numbers that is greater than one bit in length by operating on corresponding pairs of bits in parallel.

It consists of full adders connected in a chain where the output carry from each full adder is connected to the carry input of the next higher order full adder in the chain.

“A n bit parallel adder requires n full adders to perform the operation.”

Fig.: n-bit binary parallel adder

Working of n bit parallel adder 1. As shown in the figure, firstly the full adder FA1 adds A1 and B1 along with the carry C1 to

generate the sum S1 (the first bit of the output sum) and the carry C2 which is connected to the next adder in chain.

2. Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2 and B2 to generate the sum S2(the second bit of the output sum) and the carry C3 which is again further connected to the next adder in chain and so on.

3. The process continues till the last full adder FAn uses the carry bit Cn to add with its input An and Bn to generate the last bit of the output along last carry bit Cout.

4.5 Binary Parallel Subtractor (2’s Complement Adder)

A Parallel Subtractor is a digital circuit capable of finding the arithmetic difference of two binary numbers that is greater than one bit in length.

The parallel subtractor can be designed in several ways including combination of half and full subtractors, all full subtractors or all full adders with subtrahend complement input. “A n bit parallel subtractor requires n full adders & n NOT gates to perform the operation.”

Fig.: n-bit binary parallel subtractor

(“1”)


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Working of Parallel Subtractor – 1. As shown in the figure, the parallel binary subtractor is formed by combination of all full

adders with subtrahend complement input. 2. Firstly the 1’s complement of B is obtained by the NOT gate and 1 can be added through

the carry to find out the 2’s complement of B. This is further added to A to carry out the arithmetic subtraction.

3. The process continues till the last full adder FAn uses the carry bit Cn to add with its input An and 2’s complement of Bn to generate the last bit of the output along last carry bit Cout.

4.6 Binary Parallel Adder/Subtractor (2’s Complement Adder)

Fig.: n-bit binary parallel adder/subtractor

Here M-line acts as a control line

For M = 0 (Adder):

When M=0, then one of the input to each and every XOR gate would be logic 0. This means that the XOR outputs in this case will be unchanged binary bits of the number BnBn-1…B2B1.

In addition, if M = 0, the carry in pin (Ci1) of the first full adder (FA1) would also be 0. Due to these conditions, the circuit shown will be behave as a n-bit adder adding the number AnAn-

1…A2A1 with BnBn-1…B2B1.

For M = 1 (Subtractor):

When M = 1, one of the inputs to each XOR gate would be logic 1. This means that we get the complement of the bits BnBn-1…B2 and B1 as the outputs of each XOR gate.

In addition, for the same case, even the Ci1 of the first full adder FA1 would be logically high. As a result, the cascaded arrangement of full adders shown in Fig. effectively performs-bit binary subtraction where the binary number BnBn-1…B2B1 is subtracted from AnAn-1…A2A1.

4.6.1 Advantages of Parallel Adder/Subtractor

1. The parallel adder/subtractor performs the addition/subtraction operation faster as compared to serial adder/subtractor.

2. Time required for addition/subtraction does not depend on the number of bits. 3. The output is in parallel form i.e all the bits are added/subtracted at the same time. 4. It is less costly.


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4.6.2 Disadvantages of Parallel Adder/Subtractor

1. Each adder/subtractor has to wait for the carry/borrow which is to be generated from the previous adder in chain.

2. The propagation delay (delay associated with the travelling of carry bit) is increase with the increase in the number of bits to be added/subtract.

4.7 BCD Adder/Decimal Adder

BCD adder is combinational circuit that adds two BCD number and gives output also in BCD.

Add two BCD numbers using ordinay binary addition.

If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form.

If the four-bit sum is > 9 or if a carry is generated from the four-bit sum, the sum is invalid.

To correct the invalid sum, add 01102 to the four-bit sum. If a carry results from this addition, add it to the next higher-order BCD digit.

Thus to implement BCD adder we require :

4-bit binary adder for initial addition.

Logic circuit to detect sum greater than 9 and,

One more 4-bit adder to add 01102 in the sum if sum is greater than 9 or carry is 1.

The logic circuit to detect sum > 9 can be determined by simplifying the Boolean expression of given truth table

Inputs Output Carry

Z3 Z2 Z1 Z0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1


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K-Map representation of truth table:

Design of logic circuit:

4.8 Carry Look Ahead Adder

In parallel adder, the carry propagation time is the major speed limiting factor.

One widely used approach employs the principle of carry look-ahead solves this problem by calculating the carry signals in advance, based on the input signals.

This type of adder circuit is called as carry look-ahead adder (CLA adder). It is based on the fact that a carry signal will be generated in two cases: (1) When both bits Ai and Bi are 1, or (2) When one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.

To understand the carry propagation problem, let’s consider the case of adding two n-bit numbers A and B.

The Figure shows the full adder circuit used to add the operand bits in the ith column; namely

Ai & Bi and the carry bit coming from the previous column (Ci).


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Gi is known as the carry Generate signal since a carry (Ci+1) is generated whenever Gi =1, regardless of the input carry (Ci).

Pi is known as the carry propagate signal since whenever Pi =1, the input carry is propagated to the output carry, i.e., Ci+1. = Ci (note that whenever Pi =1, Gi =0).

Computing the values of Pi and Gi only depend on the input operand bits (Ai & Bi).

Fig.: Carry look ahead adder

The Boolean expression of the carry outputs of various stages can be written as follows:

In general, the ith Carry output is expressed in the form Ci = Fi (P’s, G’s, C0).


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Fig.: Combination circuit to generate c1, c2, c3,…

4.9 Magnitude Comparator

It compares two numbers A & B.

In process of comparison, it first compares MSB of input A to MSB of input B.

If one of these bits is 1 and the other 0, the process is completed & the number containing 1 as the MSB is identified as the largest number.

If MSB of A equals the MSB of B, then the next most significant bits of A and B are compared.

This process continues until a bit of one number differs from the corresponding bit of the other. 4.9.1 2 bit Magnitude Comparator

There are two numbers A and B, each of two bits long.

Magnitude comparator compares numerical values of these numbers.

The result of comparison can be Equal (E), Greater than (G) or Less than (L).

If A > B then G should be asserted to 1.

If A = B then E should be asserted to 1.

If A < B then L should be asserted to 1.

Fig.: Block diagram of magnitude comparator


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Truth Table

Inputs Outputs

A1 A0 B1 B0 G E L

0 0 0 0 0 1 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 1 0 0

0 1 0 1 0 1 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 1 0

1 0 1 1 0 0 1

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 1 0

Boolean Equation

For E,

For L,

For G,

Circuit Diagram


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4.9.2 4 bit Magnitude Comparator

Fig.: Circuit diagram of 4 bit magnitude comparator


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4.10 Encoder

It is a combinational circuit.

It has ‘n’ input lines & ‘m’ output lines. (2m = n, where n = inputs and m = outputs)

An encoder produces an ‘m’ bit binary code corresponding to the digital input number of ‘n’ bits.

Many types of Encoders – Octal to Binary (8 to 3), Decimal to BCD (10 to 4) etc.

The block diagram is shown as below,

Fig.: Block diagram of encoder

4.10.1 8 to 3 (Octal to Binary) Encoder

Truth Table: Boolean Eq.:

Input Output

D0 D1 D2 D3 D4 D5 D6 D7 Q2 Q1 Q0

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

Q0 = D1 + D3 + D5 + D7 Q1 = D2 + D3 + D6 + D7 Q2 = D4 + D5 + D6 + D7

Circuit Diagram:

It has 8 input lines & 3 output lines.

Corresponding to the eight input octal numbers we get three bit binary output.

In encoders only one input will have a one value at any given time.


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4.10.2 Priority Encoder

This is special type of encoder.

Priorities are given to the input lines.

If two or more input lines are ‘1’ at the same time, then the input line with highest priority will be considered.

Fig.: Block diagram of priority encoder

The truth table of priority encoder is as given below,

There are four inputs, D0 through D3 and outputs Y1 and Y0. Out of the four inputs D3 has the highest priority and D0 has the lowest priority.

That means if D3 = 1 then Y1Y0 = 11 irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1Y0 = 10 irrespective of other inputs.

Truth Table:

Inputs Outputs

D3 D2 D1 D0 Y1 Y0

0 0 0 0 X X

0 0 0 1 0 0

0 0 1 X 0 1

0 1 X X 1 0

1 X X X 1 1

K-Map representation of truth table:

Y1 = D3 + D2

Y0 = D3 + D2’ D1

Circuit diagram:


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4.11 Decoder

Decoder is a device which does the reverse operation of Encoder. It is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of ‘2n’ unique output lines.

Decoder is identical to a demultiplexer without any data input.

E.g.: 2 to 4 Decoder, 3 to 8 Decoder, BCD to Seven Segment Decoder.

Fig.: Block diagram of decoder

4.11.1 2 to 4 Decoder

I0 & I1 are two inputs whereas y3, y2, y1 & y0 are four outputs.

The truth table shows that each output is ‘1’ for only a specific combination of inputs.

Block Diagram: Boolean Eq.: y0 = I1I0; y1 = I1I0; y2 = I1I0; y3 = I1I0

Circuit Diagram:

Truth Table:

Inputs Output

I1 I0 y0 y1 y2 y3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Working:

According to the truth table, when I1I0=00, the output Y0 is set to ‘1’, others are ‘0’

When I1I0=01, the output Y1 is set to ‘1’, others are ‘0’

Similarly, for other input combinations, particular output is set to ‘1’ & others are ‘0’


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4.11.2 3 to 8 Decoder

Block Diagram: Boolean Eq.: Y0 = I2I1I0 Y1 = I2I1I0 Y2 = I2I1I0 Y3 = I2I1I0 Y4 = I2I1I0 Y5 = I2I1I0 Y6 = I2I1I0 Y7 = I2I1I0

Circuit Diagram:

Truth Table:

Inputs Output

I2 I1 I0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Working:

According to the truth table, when I2I1I0=000, the output Y0 is set to ‘1’, others are ‘0’

When I2I1I0=001, the output Y1 is set to ‘1’, others are ‘0’

Similarly, for other input combinations, particular output is set to ‘1’ & others are ‘0’

4.11.3 2 to 4 Decoder with Enable

Truth Table: Circuit Diagram:

Inputs Output

E I1 I0 Y0 Y1 Y2 Y3

0 X X 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

Boolean Eq.: Y0 = E I1’ I0’ ; Y1 = E I1’ I0 ; Y2 = E I1 I0’ ; Y3 = E I1 I0


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4.11.4 Examples of Decoder

(1) Implement following function using decoder: F=Σ(2,4,5,7)

(2) Implement Full adder using decoder.

(3) Design 4 to 16 decoder using 3 to 8 decoder.

Sol:

Sol: Sum = Σ(1, 2, 4, 7) Carry = Σ(3, 5, 6, 7)

Sol:

4.12 Multiplexer (MUX)

Multiplexer is a special type of combinational circuit.

The figure below shows the n x 1 multiplexer and its equivalent circuit representation.

There are ‘n’ data inputs, 1 output and ‘m’ select lines, i.e. 2m = n. A multiplexer is a digital circuit which selects one of the n data inputs and routes it to the

output. The selection of one of the n inputs is done by the select inputs

To select ‘n’ inputs, ‘m’ select lines such that 2m = n.

Depending on the digital code applied at the select inputs, one out of ‘n’ data sources is elected and transmitted to the single output.

As shown in the figure, the multiplexer acts like a digitally controlled single pole, multiple way switch.

The output gets connected to only one of the ‘n’ data inputs at given instant of time.

It is also called DATA SELECTOR.

Fig.: Illustration of multiplexer

Different types of multiplexers are available i.e. 2 to 1, 4 to 1, 8 to 1, 16 to 1 and onwards.

Multiplexers are needed in most of electronics systems. Many logical functions can be implemented using Multiplexer.


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4.12.1 2 to 1 (2 X 1 or 2:1) Multiplexer

Here 2n=2 inputs, i.e. n=1 select lines and m = 1 output.

Circuit Diagram:

Working:

When S=0, the upper AND gate will turn ON and lower AND gate will turn OFF, and so the input I0 appears in the output.

When S=1, the upper AND gate will turn OFF and lower AND gate will turn ON, and so the input I1 appears in the output.

Block Diagram:

Truth Table:

Select Line S

Output Y

0 I0

1 I1

Boolean Eq.: Y = S’I0 + SI1

4.12.2 4 to 1 Multiplexer


When S1S0=01, the input I1 is selected and routed to the output.

Similarly, when S1S0=10, then Y=I2 & when S1S0=11, then Y=I3.

Boolean Eq.: Y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3

Circuit Diagram:

Block Diagram:

Truth Table:

Select Line Output Y S1 S0

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Working:

According to the truth table, when S1S0=00, the input I0 is selected and routed to the output.


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4.12.3 8 to 1 Multiplexer


Boolean Eq.: Y = S2’S1’S0’I0 + S2’S1’S0I1 + S2’S1S0’I2 + S2’S1S0I3

+ S2S1’S0’I4 + S2S1’S0I5 + S2S1S0’I6 + S2S1S0I7

Circuit Diagram:

Truth Table:

Select Line Output Y S2 S1 S0

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

Working:

According to the truth table, when S2S1 S0=000, the input I0 is selected and routed to the output.

When S2S1S0=001, the input I1 is selected and routed to the output.

Similarly, for other combinations of select lines particular input is routed to the output.

4.12.4 Examples of Multiplexer

(1) 8 X 1 Multiplexer using 4 X 1 and 2 X 1 Multiplexers. Sol:

MUX1 & MUX2 are 4 X 1 Multiplexer & MUX3 is 2 X 1 Multiplexer.

Assuming that input I5 is to be routed through the output.

So select lines will be S2S1S0=101.

Now, for MUX1 & MUX2, S1S0=01, so the inputs I1 & I5 will be routed through each 4 X 1 Multiplexer.

I1 & I5 appears as input to 2 X 1 Multiplexer.

The value of S2=1, so the second input which I5 will be routed through the output Y.


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(2) Implement the function F(x, y, z) = ∑ (1, 2, 6, 7) using multiplexer. Sol:

(3) Design full adder using multiplexer. Sol:

(4) Implement the following function F(x,y,z)=∑ (1,2,6,7) using 4 X 1 mux.

(5) Implement the following function F (A, B, C, D) = ∑ (1, 3, 4, 11, 12, 13, 14, 15) using 8 X 1 multiplexer.

Sol: Sol:


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4.13 Demultiplexer (DEMUX)

Fig.: Illustration of demultiplexer

It has one input common data, ‘n’ select lines and ‘m’ output lines.

A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs.

At a time only one output line is selected by the select lines and the input is transmitted to the selected output line.

Relation between ‘n’ output lines and m select lines is as follows :

n = 2m 4.13.1 1 X 4 Demultiplexer

1 to 4 Demultiplexer has one data input F; select line inputs a, b and four outputs A, B, C & D.

The select lines control the data to be routed. It helps in selecting the output on which the data will be routed.

Truth Table:

Select Line Output Line

b a

0 0 A

0 1 B

1 0 C

1 1 D

Boolean Equation:

A = Fb′a′; B = Fb′a; C = Fba′; D = Fba;

Working:

When ab=”00”, the input data F is routed to the output A

When ab=”01”, the input data F is routed to the output B

When ab=”10”, the input data F is routed to the output C

When ab=”11”, the input data F is routed to the output D

Circuit Diagram:


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4.13.2 1 X 8 Demultiplexer

1 to 8 Demultiplexer has one data input I; select line inputs are S2, S1 & S0 and eight outputs F0, F1, F2, F3, F4, F5, F6, F7 & F8.

The select lines control the data to be routed. It helps in selecting the output on which the data i.e. ‘I’ will be routed.

Truth Table:

Select Line Output Line

S2 S1 S0

0 0 0 F0

0 0 1 F1

0 1 0 F2

0 1 1 F3

1 0 0 F4

1 0 1 F5

1 1 0 F6

1 1 1 F7

Boolean Equation:

F0 = IS2S1S0

; F1 = IS2S1S0;

F2 = IS2S1S0

; F3 = IS2S1S0;

F4 = IS2S1S0; F5 = IS2S1S0;

F6 = IS2S1S0; F7 = IS2S1S0

Working:

When S2S1S0=”000”, the input data routed to the output F0








Circuit Diagram:

4.13.3 Applications of Multiplexer and Demultiplexer

1. Communication system 2. Computer memory 3. Telephone network 4. ALU in computer 5. Transmission from the commuter system of a satellite 6. Shift register etc.


24


4.14 Parity Bit Generator and Checker

Ex-OR functions are very useful in systems requiring error detection & correction codes.

Binary data, when transmitted and processed, is susceptible to noise that can alter its 1s to 0s and 0s to 1s.

To detect such errors, an additional bit called the parity bit is added to the data bits and the word containing the data bits and the parity bit is transmitted.

At the receiving end the number of 1s in the word received is counted and the error, if any, is detected.

This parity check detects only single bit errors.

The circuit that generates the parity bit in the transmitter is called a parity generator.

The circuit that checks the parity in the receiver is called parity checker.

A parity bit, a 0 or a 1 is attached to the data bits such that the total number of 1s in the word is even for even parity and odd for odd parity.

The parity bit can be attached to the code group either at the beginning or at the end depending on system design.

A given system operates with either even or odd parity but not both. So, a word always contains either an even or an odd number of 1s.

At the receiving end, if the word received has an even number of 1s in the odd parity system or an odd number of 1s in the even parity system, it implies that an error has occurred.

In order to check or generate the proper parity bit in a given code word, the basic principle used is “the modulo sum of an even number of 1s is always a 1”.

Therefore, in order to check for an error, all the bits in the received word are added.

If the modulo sum is a o for an odd parity system or a 1 for an even parity system, an error is detected.

Fig.: Circuit diagram of parity bit generator / checker


25


4.14.1 Examples of Parity Bit Generator / Checker

(1) Design 4 bit input even parity bit generator

Let the 4-bit input be A, B, C & D.

For even parity, a parity bit 1 is added such that the total number of 1s in the 4-bit input and the parity bit together is even.

Truth Table:

Boolean Equation

Circuit Diagram

(2) Design 4 bit input odd parity bit generator

An odd parity bit generator outputs a 1, when the number of 1s in the data bits is even, so that the total number of 1s in the data bits and parity bit together is odd.

Truth Table

Boolean Equation

Circuit Diagram


26


4.15 GTU Questions

Un

it

Gro

up

Questions

Sum

mer

-15

Win

ter-

15

Sum

mer

-16

Win

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Sum

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Win

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Sum

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No

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4

A Write short note on half adder and full adder. 7

4.2.1_4 4.2.2_4

A Explain a full adder circuit. 3 3

A Explain half adder circuit. Explain full adder circuit with the help of two half adders.

7

A&B Explain how four bit combined binary adder and subtractor circuit can be constructed using full adders?

7 4.6_7

B Explain full- subtractor in brief. 3 4 4.3.2_5

C Explain look-ahead-carry adder. 7 4.8_9

C Construct BCD adder using two 4-bit binary parallel adder and logic gates.

7 4.7_8

D Discuss 4 – bit magnitude comparator. 7 4.9.2_13

D Explain 2-bit magnitude comparator. 3 4.9.1_11

E Explain octal to binary encoder. 3 4.10.1_14

F Explain in brief the working of decoders. 7 4.11_16

F Explain 3-to-8 line decoder. Construct a 4 × 16 decoder with two 3 × 8 decoder. Use block diagram construction only.

7 4.11.2_17 4.11.4_18

F Describe a 3-to-8 line decoder. 7 4.11.2_17 F Draw truth table and logic diagram of 3 to 8

line decoder. 4

F&G Design a full adder circuit using decoder and multiplexer (4:1 MUX).

4 4.11.4_18 4.12.4_21

G Explain multiplexer. 7 7 4.12_18

G Implement the following Boolean function by using 8:1 MUX F(A,B,C,D) = Σm(0,1,3,4,8,9,15).

3 4.12.4_21

G Explain multiplexer with suitable example. 4 3 4.12_18

G Explain a 4 input multiplexer. 7 4.12.2_19

G Implement a full adder using 8:1 multiplexer. 7 4.12.4_21

G&H Describe multiplexer and de-multiplexer with circuit and application of each. 7

4.12_18 4.13_22

4.13.3_23

I Design 3-bit odd parity generator circuit. 4 4.14.1_25

I Explain a parity generator and checker. 4 3 4.14_24

I Design 3-bit even parity generator circuit. 4 4.14.1_25

Table of Contents€¦ · 4.8 Carry Look Ahead Adder In parallel adder, the carry propagation time...

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