Split Compilation forAccelerator-based Multicores

Panagiotis TheocharisComputer Systems Lab (CSL)

Ghent University

Problem Statement

• Ever increasing performance and power-efficiency needs

• ASICs/ASIPs are becoming unaffordable

Heterogeneous concurrency

Accelerator-based Multicores

• General purpose cores

• Specialized accelerators

Interfacing

Virtualizing the HW/SW Interface

• Reuse legacy code

• Auto-tune for efficiency

• Immune to hardware innovation

• Flexible resource allocation

Our approach: Split Compilation

Static PhaseStatic Phase Dynamic Phase

Dynamic Phase

bytecodebytecode

codecode executable

executable

annotationsannotations

Architecture description

Architecture description

• Offline• Time-consuming analyses• Hardware-independent optimizations

• Install/Load/Run time• Quick decisions• Actual code mapping

Target Hardware Platform

• Two functional views/operation modes

• Features heterogeneous FUs, local RFs, direct connections between FUs

• Reconfigurable every cycle

• Tightly coupled to control processor

IMEC ADRES CGRA Coarse-Grained Reconfigurable Array

Phase 1 (current)

OpenIMPACTOpenIMPACT DRESCDRESCIRIR

architecture descriptionarchitecture description

LLVMLLVM

Heuristical back-end

Low Level Virtual Machinecompiler infrastructure

• Replace existing simulated-annealing-based backend• Quick decision based on heuristics• Depends on code/hardware features• Parameterizable for DSE

C codeC codeADRES

executable

ADRES executabl

e

Phase 2: Design Space Exploration

LLVMLLVM DRESC +DRESC +IRIR

architecture descriptionarchitecture description

Machine Learning

Design Space Exploration

optimizedarchitecture description

optimizedarchitecture description

optimized compiler strategy

optimized compiler strategy

C codeC codeADRES

executable

ADRES executabl

e

Phase 3: Virtualization

LLVMLLVM LLVM – DRESCLLVM – DRESCC codeC codeADRES

executable

ADRES executabl

ebytecodebytecode

optimized architecture description

optimized architecture description

deployment time

compiler strategycompiler strategy

compiler strategycompiler strategy

static

ML

Phase 4: Mapping Automation

LLVMLLVM LLVM – DRESCLLVM – DRESCbytecodebytecode

deployment time

abstract architecture description

abstract architecture description

optimized architecture description

optimized architecture description

compiler strategycompiler strategy

C codeC code

static

ADRES executabl

e

ADRES executabl

e

Phase 5: True Split Compilation

LLVMLLVM LLVM – DRESCLLVM – DRESCbytecodebytecode

static deployment time

optimized architecture description

optimized architecture description

compiler strategycompiler strategy

ML

abstract architecture description

abstract architecture description

annotationsannotations

C codeC codeADRES

executable

ADRES executabl

e

Split Compilation forAccelerator-based Multicores

Panagiotis TheocharisComputer Systems Lab (CSL)

Ghent University