Signal Integrity Simulation
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Signal Integrity Simulation and high-speed ASICs David Porret PH/ESE/ME ESE Group Seminar 15/2/2011
description
Signal Integrity Simulation. and high-speed ASICs. David Porret PH/ESE/ME ESE Group Seminar 15/2/2011. Outline. The GBT SerDes ASIC The problem Building models Checking models Some results Conclusions. On-Detector Custom Electronics & Packaging Radiation Hard. Off-Detector - PowerPoint PPT Presentation
Transcript of Signal Integrity Simulation
Signal Integrity Simulation and high-speed ASICs
David Porret PH/ESE/ME
ESE Group Seminar 15/2/2011
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Outline
• The GBT SerDes ASIC• The problem• Building models• Checking models• Some results • Conclusions
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The GBT Project
• Part of the Versatile Link project : Gigabit optical link for the LHC detectors.
• Actually testing first version of the ASIC : GBT SerDes ,4.8 Gb/s serializer / deserializer.
On-DetectorCustom Electronics & Packaging
Radiation Hard
Off-DetectorCommercial Off-The-Shelf (COTS)
Custom Protocol
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The GBT SerDes ASIC
Full custom
Serialinput
DES
ClockGenerator
Clockreference
SERSerialout
Switch
Switch
120
FECDecoder
FECEncoder
De-scramblerHeader decoder
ScramblerHeader encoder
ParallelOut/
BERT
ParallelIn/
PRBS
ControlLogic
PhaseShifter
Switch
Switch
120
Switch
Switch
120
120
120
120
120
txDataValid
dIn [29:0]
Full custom
txClock40
txClock160
rxDataValiddOut [29:0]
rxClock40
rxClock160
PROMPT
I2C
JTAG
AUX[n:0]
RX: 40 MHz & 160 MHz
TX: 40 MHz & 160 MHz
Data path
Clocks
Control bus
Data path
Clocks
Control bus
RST
rxRdy
txRdy
ClkOut3
ClkOut2
ClkOut1
ClkOut0
120
120
120
120
120
120120
FrameAligner
120
=
130 nm CMOS technology4x4 mm silicon die12x12 mm 121 pins BGA Package “open”
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The problem (1)
Conclusions from the TWEPP 2010 presentation Almost all of the functions proved 100% functional (…) For the De-serializer
– The clock recovery function works fine over the full range– However, error free data reception at 4.8 Gb/s has not (yet?) been achieved!
• OK up to 2.4 Gb/s
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The problem (2)
Silicon DieBGA Package
Rx Termination
Rx Diff. Pair
Tx Diff. Pair
EDA-02085 TEST BOARD
Top
BGA PACKAGE
GBT SerDesSMA to SFP+ adapter MECT connector
Termination
Optical TRX SFP
Probe Effect ?Test board ?Package ?Chip Design ?
4.8 Gb/s Frame
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Building models
Ansoft Designer
S ParametersS P
aram
eter
s
S Parameters
Equivalent circuit
Spice Netlist
HSpice Netlist
SIwave
SIwave SIwave (2.5D)
HFSS (3D)
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Full Setup in simulator
SMA-SFP Adapter
MECT Connector
EDA-02086
Termination
Agilent probe
GBT Receiver
Package
00
0
0
0
0
0
RXINPUTN_R1_2
RXINPUTN_U3_H2
RXINPUTP_R1_1
RXINPUTP_U3_J2
RXINPUTN_U1_A11
RXINPUTP_U1_A12
ref
100
R32
1.2e-010
L33
3.92e-014farad
C34
ID=
35
ID=40
GBPS_RX_N_J5_12|RD-
GBPS_RX_P_J5_13|RD+
GBPS_RX_N_IC5_H2|RXINPUTN
GBPS_RX_P_IC5_J2|RXINPUTP
ref
VplusVminus
12GHZ probe6
ID=107RD_N_SMA
RD_P_SMA
RD_N_MECT
RD_P_MECT
ref
0.4
95
pF
C1
17
0.4
69
pF
C1
33
0.0
06
5p
F
C1
36
ID=
15
4
20
k
R1
92
1 2
3
1 2
3
EDA-02085 TEST BOARD
Top
BGA PACKAGE
GBT SerDesSMA to SFP+ adapter MECT connector
Termination
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Checking models (1) Unpopulated board
Measurement (yellow) and simulation (blue) with 100 ohms termination at the BGA pads
Frequency domain simulation
Dielectric losses
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Checking models(2)Full Setup
Probe is at the receiver termination , ≈ 3.5 mm from the input buffer.Measurement (yellow) and Simulation (Brown).
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Checking models(3)TDR
0 200000 400000 600000 800000 1000000 12000000
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
Zdiff (measurement) zdiff (simulation) [ohm]
SMA
MECT con-nec-tors
Package and Die
Zdiff (ohms)
ns
Probe removedMultiples comparisons show same behaviour but different absolute values
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Conclusions on models
• With experience models could be better.• 3D EM models are more accurate but the
simulator runs all the night and (good) results are not always there. 2,5D solver is a good compromise.
• The main error source is the interconnections between models. Always check model physical boundaries and frequency domain.
• Effects of solder joints ?
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Checking the probe effect
Probe (gray) No Probe (blue)
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“Virtual Probing”1Gbps 3.2Gbps 4.8Gbps
Termination
Rx Input buffer
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Improving the package
Dark blue = original design
Move the termination close to the input buffer
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Conclusions (1)For our problem
• Probing at the termination is misleading, the signals at the input buffer are not that bad.
• But things can be improved :– around the MECT connector on the testboard.
(for future layout).– in the package by moving the termination and
optimizing the layout.
• Linear frequency domain simulation shows package resonances ?
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Conclusions(2)SI tools
• Much easier with CERN recently acquired software (Ansoft Designer + SIWave).
• Well integrated in Cadence. • What-if simulations. • De-embedding of VNA measurements.• Also Power Integrity and EMC features,
optimize decoupling.
