Sequential Logic Review

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Sequential Logic Review

Material in this review is from Contemporary Logic Design by Randy Katz

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C1 C2 C3

comparator

value(4 bits)

equal

multiplexer

reset

open/closed

new equal

mux control

clock

comb. logic

state

Sequential Circuits

• Circuits with Feedback– Outputs = f(inputs, past inputs, past outputs)– Basis for building "memory" into logic circuits– Door combination lock is an example of a sequential circuit

• State is memory

• State is an "output" and an "input" to combinational logic

• Combination storage elements are also memory

Ld1 Ld2 Ld3

Reg: C1, C2, C3need a clock to loadvalue

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Digital combination lock state diagram

• States: 5 states

– represent point in execution of machine

– each state has outputs

• Transitions: 6 from state to state, 5 self transitions, 1 global

– changes of state occur when clock says its ok

– based on value of inputs

• Inputs: reset, new, results of comparisons

• Output: open/closed

closed closedclosedC1==value

& newC2==value

& newC3==value

& new

C1!=value& new C2!=value

& newC3!=value

& new

closed

reset

not newnot newnot newi.e., no digits entered

S1 S2 S3 OPEN

ERR

open

4

Q

D

Clk=1

R

S

0

D’

0

D’ D

Q’

negative edge-triggered D flip-flop (D-FF)

4-5 gate delays

must respect setup and hold time constraints to successfully

capture input

characteristic equationQ(t+1) = D

holds D' whenclock goes low

holds D whenclock goes low

Edge-Triggered Flip-Flops

• Sensitive to inputs only near edge of clock signal (not while high)

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Q

D

Clk=0

R

S

D

D’

D’

D’ D

when clock goes high-to-lowdata is latched

when clock is lowdata is held

Edge-Triggered Flip-Flops (cont’d)

• Step-by-step analysis

Q

new D

Clk=0

R

S

D

D’

D’

D’ D

new D old D

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positive edge-triggered FF

negative edge-triggered FF

D

CLK

Qpos

Qpos'

Qneg

Qneg'

100

Edge-Triggered Flip-Flops (cont’d)

• Positive edge-triggered– Inputs sampled on rising edge; outputs change after rising edge

• Negative edge-triggered flip-flops– Inputs sampled on falling edge; outputs change after falling

edge

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Timing Methodologies

• Rules for interconnecting components and clocks– Guarantee proper operation of system when strictly followed

• Approach depends on building blocks used for memory elements– Focus on systems with edge-triggered flip-flops

• Found in programmable logic devices– Many custom integrated circuits focus on level-sensitive latches

• Basic rules for correct timing:– (1) Correct inputs, with respect to time, are provided to the flip-

flops– (2) No flip-flop changes state more than once per clocking event

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there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

clock

datachangingstable

input

clock

Tsu Th

clock

dataD Q D Q

Timing Methodologies (cont’d)

• Definition of terms– clock: periodic event, causes state of memory element to

change; can be rising or falling edge, or high or low level– setup time: minimum time before the clocking event by

which the input must be stable (Tsu)– hold time: minimum time after the clocking event until which

the input must remain stable (Th)

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behavior is the same unless input changeswhile the clock is high

D Q

CLK

positiveedge-triggered

flip-flop

D QG

CLK

transparent(level-sensitive)

latch

D

CLK

Qedge

Qlatch

Comparison of Latches and Flip-Flops

10all measurements are made from the clocking event that is,

the rising edge of the clock

Typical Timing Specifications

• Positive edge-triggered D flip-flop– Setup and hold times– Minimum clock width– Propagation delays (low to high, high to low, max and

typical)Th

0.5ns

Tw 3.3ns

Tplh3.6ns1.1ns

Tphl3.6ns1.1ns

Tsu1.8ns

D

CLK

Q

Tsu1.8ns

Th0.5ns

data from374 posedgetriggeredflip flop

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IN

Q0

Q1

CLK

100

Cascading Edge-triggered Flip-Flops

• Shift register– New value goes into first stage– While previous value of first stage goes into second stage– Consider setup/hold/propagation delays (prop must be >

hold)

CLK

INQ0 Q1

D Q D Q OUT

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timing constraintsguarantee proper

operation ofcascaded components

assumes infinitely fast distribution of the clock

Cascading Edge-triggered Flip-Flops (cont’d)

• Why this works– Propagation delays exceed hold times– Clock width constraint exceeds setup time– This guarantees following stage will latch current value

before it changes to new value

Tsu

4ns

Tp

3ns

Th

2ns

In

Q0

Q1

CLK

Tsu

4ns

Tp

3ns

Th

2ns

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original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

CLK1 is a delayedversion of CLK0

In our design we expectCLK1 and CLK0 arrive

at the same time

In

Q0

Q1

CLK0

CLK1

100

Clock Skew

• The problem– Correct behavior assumes next state of all storage elements

determined by all storage elements at the same time– This is difficult in high-performance systems because time

for clock to arrive at flip-flop is comparable to delays through logic

– Effect of skew on cascaded flip-flops:

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Summary of Latches and Flip-Flops

• Development of D-FF– Level-sensitive used in custom integrated circuit– Edge-triggered used in programmable logic devices– Good choice for data storage register

• Historically J-K FF was popular but now never used– Similar to R-S but with 1-1 being used to toggle output

(complement state)– Good in old days of TTL/SSI (more complex input function:

D = JQ' + K'Q– Not a good choice for PALs/PLAs as it requires 2 inputs– Can always be implemented using D-FF

• Preset and clear inputs are highly desirable on flip-flops– Used at start-up or to reset system to a known state

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D DQ Qasynchronous

inputsynchronized

input

synchronous system

Clk

Dealing with Synchronization Failure

• Probability of failure can never be reduced to 0, but it can be reduced– (1) slow down the system clock: this gives the synchronizer

more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems

– (2) use fastest possible logic technology in the synchronizer

– (3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail)

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D Q

D Q

Q0

Clock

Clock

Q1

Async Input

D Q

D Q

Q0

Clock

Clock

Q1

Async Input D Q

Clocked Synchronous

System

Synchronizer

Handling Asynchronous Inputs

• Never allow asynchronous inputs to fan-out to more than one flip-flop– Synchronize as soon as possible and then treat as

synchronous signal

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In is asynchronous and fans out to D0 and D1

one FF catches the signal, one does not

inconsistent state may be reached!

In

Q0

Q1

CLK

Handling Asynchronous Inputs (cont’d)

• What can go wrong?– Input changes too close to clock edge (violating setup time

constraint)

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R S R S R S

D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

IN1 IN2 IN3 IN4

R S

"0"

Registers

• Collections of flip-flops with similar controls and logic– Stored values somehow related (e.g., form binary value)– Share clock, reset, and set lines– Similar logic at each stage

• Examples– Shift registers– Counters

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D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Shift Register

• Holds samples of input– Store last 4 input values in sequence– 4-bit shift register:

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clear sets the register contentsand output to 0

s1 and s0 determine the shift function

s0 s1 function0 0 hold state0 1 shift right1 0 shift left1 1 load new input

left_inleft_out

right_out

clearright_in

output

input

s0s1

clock

Universal Shift Register

• Holds 4 values– Serial or parallel inputs– Serial or parallel outputs– Permits shift left or right– Load new input

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Nth cell

s0 and s1control mux0 1 2 3

D

Q

CLK

CLEAR

Q[N-1](left)

Q[N+1](right)

Input[N]

to N-1th cell

to N+1th cell

clears0 s1 new value1 – – 00 0 0 output0 0 1 output value of FF to left (shift right)0 1 0 output value of FF to right (shift left)0 1 1 input

Design of Universal Shift Register

• Consider one of the four flip-flops– New value at next clock cycle:

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D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

OUT

Pattern Recognizer

• Combinational function of input samples– In this case, recognizing the pattern 1001 on the single input

signal

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D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

Counters

• Sequences through a fixed set of patterns– In this case, 1000, 0100, 0010, 0001– If one of the patterns is its initial state (by loading or

set/reset)

• Mobius (or Johnson) counter– In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000

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D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

"1"

Binary Counter

• Logic between registers (not just multiplexer)– XOR decides when bit should be toggled– Always for low-order bit, only when first bit is true for

second bit, and so on

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EN

DCBA

LOAD

CLK

CLR

RCO

QDQCQBQA

"1"

"0""0""0""0"

"0"

EN

DCBA

LOAD

CLK

CLR

RCO

QDQCQBQA

"1"

"0""1""1""0"

Offset Counters

• Starting offset counters – use of synchronous load– e.g., 0110, 0111, 1000, 1001, 1010,

1011, 1100, 1101, 1111, 0110, . . .

• Ending offset counter – comparator for ending value– e.g., 0000, 0001, 0010, ..., 1100,

1101, 0000

• Combinations of the above (start and stop value)

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State Machine Model

• Values stored in registers represent the state of the circuit• Combinational logic computes:

– Next state• Function of current state and inputs

– Outputs• Function of current state and inputs (Mealy machine)• Function of current state only (Moore machine)

Inputs

Outputs

Next State

Current State

outputlogic

next statelogic

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State Machine Model (cont’d)

• States: S1, S2, ..., Sk• Inputs: I1, I2, ..., Im• Outputs: O1, O2, ..., On• Transition function: Fs(Si, Ij)• Output function: Fo(Si) or Fo(Si, Ij)

Inputs

Outputs

Next State

Current State

outputlogic

next statelogic

Clock

Next State

State

0 1 2 3 4 5

28state feedback

inputs

outputsreg

combinational logic for

next state logic foroutputs

inputs outputs

state feedback

regcombinational

logic fornext state

logic foroutputs

Comparison of Mealy and Moore Machines

• Mealy Machines tend to have less states– Different outputs on arcs (n^2) rather than states (n)

• Moore Machines are safer to use– Outputs change at clock edge (always one cycle later)– In Mealy machines, input change can cause output change

as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback

• Mealy Machines react faster to inputs– React in same cycle – don't need to wait for clock– In Moore machines, more logic may be necessary to decode

state into outputs – more gate delays after

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VendingMachine

FSM

N

D

Reset

Clock

OpenCoinSensor

ReleaseMechanism

Example: Vending Machine

• Release item after 15 cents are deposited• Single coin slot for dimes, nickels• No change

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Example: Vending Machine (cont’d)

• Suitable Abstract Representation– Tabulate typical input sequences:

• 3 nickels• nickel, dime• dime, nickel• two dimes

– Draw state diagram:• Inputs: N, D, reset• Output: open chute

– Assumptions:• Assume N and D asserted

for one cycle• Each state has a self loop

for N = D = 0 (no coin)

S0

Reset

S2

D

S6[open]

D

S4[open]

D

S1

N

S3

N

S7[open]

N

S5[open]

N

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• Minimize number of states - reuse states whenever possible

symbolic state table

present inputs next outputstate D N state open 0¢ 0 0 0¢ 0

0 1 5¢ 01 0 10¢ 01 1 – –

5¢ 0 0 5¢ 00 1 10¢ 01 0 15¢ 01 1 – –

10¢ 0 0 10¢ 00 1 15¢ 01 0 15¢ 01 1 – –

15¢ – – 15¢ 1

0¢

Reset

5¢

N

N

N + D

10¢

D

15¢[open]

D

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present stateinputs next state outputQ1 Q0 D N D1 D0 open

0 0 0 0 0 0 00 1 0 1 01 0 1 0 01 1 – – –

0 1 0 0 0 1 00 1 1 0 01 0 1 1 01 1 – – –

1 0 0 0 1 0 00 1 1 1 01 0 1 1 01 1 – – –

1 1 – – 1 1 1


• Uniquely Encode States, binary encoding is selected

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D1 = Q1 + D + Q0 N

D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D

OPEN = Q1 Q0


• Mapping to Logic0 0 1 1

0 1 1 1

X X X X

1 1 1 1

Q1D1

Q0

N

D

0 1 1 0

1 0 1 1

X X X X

0 1 1 1

Q1D0

Q0

N

D

0 0 1 0

0 0 1 0

X X X X

0 0 1 0

Q1Open

Q0

N

D

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present state inputs next state outputQ3Q2 Q1Q0 D N D3 D2 D1 D0 open0 0 0 1 0 0 0 0 0 1 0

0 1 0 0 1 0 01 0 0 1 0 0 01 1 - - - - -

0 0 1 0 0 0 0 0 1 0 00 1 0 1 0 0 01 0 1 0 0 0 01 1 - - - - -

0 1 0 0 0 0 0 1 0 0 00 1 1 0 0 0 01 0 1 0 0 0 01 1 - - - - -

1 0 0 0 - - 1 0 0 0 1

D0 = Q0 D’ N’

D1 = Q0 N + Q1 D’ N’

D2 = Q0 D + Q1 N + Q2 D’ N’

D3 = Q1 D + Q2 D + Q2 N + Q3

OPEN = Q3


• One-hot Encoding

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Equivalent Mealy and Moore State Diagrams

Moore machine

outputs associated with state

0¢[0]

10¢[0]

5¢[0]

15¢[1]

N’ D’ + Reset

D

D

N

N+D

N

N’ D’

Reset’

N’ D’

N’ D’

Reset

Mealy machineoutputs associated with transitions

0¢

10¢

5¢

15¢

(N’ D’ + Reset)/0

D/0

D/1

N/0

N+D/1

N/0

N’ D’/0

Reset’/1

N’ D’/0

N’ D’/0

Reset/0

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Vending Machine (cont’d)

• OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change

• This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay

• OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)

• Implementation now looks like a synchronous Mealy machine– Common for programmable devices to have FF at end of

logic

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Finite State Machine Optimization

• State Minimization– Fewer states require fewer state bits– Fewer bits require fewer logic equations

• Encodings: State, Inputs, Outputs– State encoding with fewer bits has fewer equations to implement

• However, each may be more complex– State encoding with more bits (e.g., one-hot) has simpler

equations• Complexity directly related to complexity of state diagram

– Input/output encoding may or may not be under designer control

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Algorithmic Approach to State Minimization

• Goal – identify and combine states that have equivalent behavior

• Equivalent States:

– Same output

– For all input combinations, states transition to same or equivalent states

• Algorithm Sketch

– 1. Place all states in one set

– 2. Initially partition set based on output behavior

– 3. Successively partition resulting subsets based on next state transitions

– 4. Repeat (3) until no further partitioning is required

• states left in the same set are equivalent

– Polynomial time procedure

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Input Next State OutputSequence Present StateX=0 X=1 X=0 X=1

Reset S0 S1 S2 0 00 S1 S3 S4 0 01 S2 S5 S6 0 000 S3 S0 S0 0 001 S4 S0 S0 1 010 S5 S0 S0 0 011 S6 S0 S0 1 0

State Minimization Example

• Sequence Detector for 010 or 110

S0

S3

S2S1

S5 S6S4

1/00/0

1/0

1/00/1

0/01/00/0

1/00/0

1/00/1

1/00/0

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( S0 S1 S2 S3 S4 S5 S6 )

( S0 S1 S2 S3 S5 ) ( S4 S6 )

( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 )

( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )

Input Next State OutputSequence Present StateX=0 X=1 X=0 X=1

Reset S0 S1 S2 0 00 S1 S3 S4 0 01 S2 S5 S6 0 000 S3 S0 S0 0 001 S4 S0 S0 1 010 S5 S0 S0 0 011 S6 S0 S0 1 0

S1 is equivalent to S2



Method of Successive Partitions

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Input Next State OutputSequence Present State X=0 X=1 X=0 X=1

Reset S0 S1' S1' 0 00 + 1 S1' S3' S4' 0 0X0 S3' S0 S0 0 0X1 S4' S0 S0 1 0

Minimized FSM

• State minimized sequence detector for 010 or 110

S0

S1’

S3’ S4’

X/0

1/0

1/00/1

0/0

X/0

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symbolic state transition table

present next state output state 00 01 10 11 S0 S0 S1 S2 S3 1 S1 S0 S3 S1 S4 0 S2 S1 S3 S2 S4 1 S3 S1 S0 S4 S5 0 S4 S0 S1 S2 S5 1 S5 S1 S4 S0 S5 0

inputs here

More Complex State Minimization

• Multiple input example

1001

11

00

00

01

1110

10

01

1100

1000

11

00

1110

01

10

1101

00

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

01

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S0-S1 S1-S3 S2-S2 S3-S4

S0-S0 S1-S1 S2-S2 S3-S5

S0-S1 S3-S0 S1-S4 S4-S5

S0-S1 S3-S4 S1-S0 S4-S5

S1-S0 S3-S1 S2-S2S4-S5

S4-S0S5-S5

S1-S1 S0-S4

minimized state table(S0==S4) (S3==S5)

present next state output state 00 01 10 11 S0' S0' S1 S2 S3' 1 S1 S0' S3' S1 S3' 0 S2 S1 S3' S2 S0' 1 S3' S1 S0' S0' S3' 0

Minimized FSM

• Implication Chart Method– Cross out incompatible states based on outputs– Then cross out more cells if indexed chart entries are

already crossed out

S1

S2

S3

S4

S5

S0 S1 S2 S3 S4

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State Assignment Strategies

• Possible Strategies– Sequential – just number states as they appear in the state table– Random – pick random codes– One-hot – use as many state bits as there are states (bit=1 –>

state)– Output – use outputs to help encode states– Heuristic – rules of thumb that seem to work in most cases

• No guarantee of optimality – another intractable problem

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One-hot State Assignment

• Simple– Easy to encode, debug

• Small Logic Functions– Each state function requires only predecessor state bits as input

• Good for Programmable Devices– Lots of flip-flops readily available– Simple functions with small support (signals its dependent upon)

• Impractical for Large Machines– Too many states require too many flip-flops– Decompose FSMs into smaller pieces that can be one-hot encoded

• Many Slight Variations to One-hot– One-hot + all-0

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I Q Q+ Oi a c ji b c k

I Q Q+ Oi a b jk a c l

I Q Q+ Oi a b ji c d j

c = i * a + i * b

b = i * ac = k * a

j = i * a + i * cb = i * ad = i * c

i / j i / k

a b

c

a

b c

i / j k / l

b d

i / ja c

i / j

Heuristics for State Assignment

• Adjacent codes to states that share a common next state

– Group 1's in next state map

• Adjacent codes to states that share a common ancestor state – Group 1's in next state map

• Adjacent codes to states that have a common output behavior

– Group 1's in output map

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Output-Based Encoding

• Reuse outputs as state bits - use outputs to help distinguish states– Why create new functions for state bits when output can

serve as well– Fits in nicely with synchronous Mealy implementations

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Current State Assignment Approaches

• For tight encodings using close to the minimum number of state bits– Heuristic approaches are not even close to optimality– Used in custom chip design

• One-hot encoding– Easy for small state machines– Generates small equations with easy to estimate complexity– Common in FPGAs and other programmable logic

• Output-based encoding– Ad hoc - no tools– Most common approach taken by human designers– Yields very small circuits for most FSMs

Sequential Logic Review

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